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參數(shù)資料
| 型號： | ADF4117BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | BATT LITHIUM COIN 3V 48MAH COIN-W/LEGS 12.5MM |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC20 |
| 封裝： | CSP-20 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ADF4117BCP |
ADF4116/ADF4117/ADF4118
–
5
–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
FL
O
Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter band-
width. This will speed up locking of the PLL.
Charge Pump Output. When enabled, this provides the
±
I
CP
to the external loop filter, which in turn drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path for the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF. See Figure 22.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 k
. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal
oscillator or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V,
it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.
2
CP
3
4
5
CPGND
AGND
RF
IN
B
6
7
RF
IN
A
AV
DD
8
REF
IN
9
10
DGND
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DV
DD
16
V
P
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
FL
O
V
P
ADF4116
ADF4117
ADF4118
CP
DV
DD
CPGND
MUXOUT
AGND
LE
RF
IN
B
DATA
RF
IN
A
CLK
AV
DD
CE
REF
IN
DGND
Chip Scale Package
TOP VIEW
(Not to Scale)
CPGND
AGND
AGND
RF
IN
B
RF
IN
A
MUXOUT
LE
DATA
CLK
CE
ADF4116
ADF4117
ADF4118
C
F
O
V
P
D
D
D
D
A
D
A
D
R
I
D
D
1
2
3
4
5
15
14
13
12
11
2
1
1
1
1
6
7
8
9
1
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| ADF4117BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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