- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9112 > ADF4106BRUZ-RL (Analog Devices Inc)IC PLL FREQ SYNTHESIZER 16TSSOP PDF資料下載
參數(shù)資料
| 型號： | ADF4106BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4106EBZ1-ND - BOARD EVAL FOR ADF4106 |
Data Sheet
ADF4106
Rev. E | Page 11 of 24
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the
phase and frequency difference between them. Figure 20 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the reference counter latch, ABP2 and ABP1, control the
width of the pulse. See Table 7.
HI
D1
D2
Q1
Q2
CLR2
CP
U1
U2
UP
DOWN
ABP2
ABP1
CPGND
U3
R DIVIDER
PROGRAMMABLE
DELAY
N DIVIDER
VP
CHARGE
PUMP
02720-020
CLR1
Figure 20. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4106 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector cycles is less than
15 ns. With LDP set to 1, five consecutive cycles of less than
15 ns are required to set the lock detect. It stays set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock is detected, this output is high with narrow, low-
going pulses.
02720-021
DGND
DVDD
CONTROL
MUX
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUXOUT
Figure 21. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4106 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Table 6 shows a summary of how
the latches are programmed.
Table 5. C1, C2 Truth Table
Control Bits
C2
C1
Data Latch
0
R Counter
0
1
N Counter (A and B)
1
0
Function Latch (Including Prescaler)
1
Initialization Latch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M83723/74W20287 | CONN RCPT 28POS JAM NUT W/PINS |
| ADF4007BCPZ-RL | IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| ADF4001BRU-REEL7 | IC CLOCK GEN PLL 16-TSSOP |
| CS2300CP-CZZR | IC CLK MULT CTRL PT LCO 10-MSOP |
| VE-2TL-IV | CONVERTER MOD DC/DC 28V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4106SCPZ-EP | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ADF4106SCPZ-EP-R7 | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4106SP1BRU-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4106SRU-EP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single Up to 325MHz 16-Pin TSSOP 制造商:Analog Devices 功能描述:6GHZ PLL SYNTHESIZER - Rail/Tube 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL 6GHZ PLL SYNTHESIZER |
| ADF4106SRU-EP-R7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single Up to 325MHz 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:6GHZ PLL SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC PLL FREQ SYNTHESIZER 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL 6GHZ PLL SYNTHESIZER |
發(fā)布緊急采購，3分鐘左右您將得到回復。