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參數(shù)資料
| 型號(hào)： | ADF4007BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類(lèi)型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 7.5GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4007EBZ1-ND - BOARD EVALUATION FOR ADF4007EB1 |
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Data Sheet
ADF4007
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
M1
15 MUXOUT
M2
N1
11 N2
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CONNECTED TO GROUND.
AGND
2
AGND
RFINB
5
RFINA
7
A
V
DD
6
A
V
DD
8
RE
F
IN
9
DG
ND
10
DG
ND
19
R
SET
20
C
P
18
V
P
17
DV
DD
16
DV
DD
TOP
VIEW
ADF4007
04537-
002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. The ground return path of the charge pump.
2, 3
AGND
Analog Ground. The ground return path of the prescaler.
4
RF
INB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5
RF
INA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7
AV
DD
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD must be the same value as DVDD.
8
REF
IN
Reference Input. A CMOS input with a nominal threshold of V
DD/2 and a dc equivalent input resistance of 100 k.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10
DGND
Digital Ground.
11, 12
N2, N1
These two bits set the N value. See Table 4.
13, 14
M2, M1
These two bits set the status of MUXOUT and PFD polarity. See Table 5.
15
MUXOUT
This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
16, 17
DV
DD
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD must be the same value as AVDD.
18
V
P
Charge Pump Power Supply. This pin should be greater than or equal to V
DD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19
R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the R
SET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
Therefore, if R
SET = 5.1 k, then ICP = 5 mA.
20
CP
Charge Pump Output. When enabled, this pin provides ±I
CP to the external loop filter, which in turn drives the
external VCO.
21
EP
Exposed Pad.
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