AVDD = DV
參數(shù)資料
型號(hào)： ADF4007BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 0K
描述： IC DIVIDER/PLL SYNTHESZR 20LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 時(shí)鐘/頻率合成器，RF
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 7.5GHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADF4007EBZ1-ND - BOARD EVALUATION FOR ADF4007EB1
Data Sheet
ADF4007
Rev. B | Page 3 of 16
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 ,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RF
IN)
1.0/7.0
GHz min/max
RF input level: +5 dBm to 10 dBm
RF Input Frequency
0.5/7.5
GHz min/max
RF input level: +5 dBm to 5 dBm, for lower frequencies,
ensure that slew rate (SR) > 560 V/s
REF
IN CHARACTERISTICS
REF
IN Input Sensitivity
0.8/V
DD
V p-p min/max
Biased at AV
DD/2
REF
IN Input Frequency
20/240
MHz min/max
For f < 20 MHz, use square wave (slew rate > 50 V/s)
REF
IN Input Capacitance
10
pF max
REF
IN Input Current
±100
A max
PHASE DETECTOR
Phase Detector Frequency3
120
MHz max
MUXOUT
MUXOUT Frequency3
200
MHz max
C
L = 15 pF
CHARGE PUMP
I
CP Sink/Source
5.0
mA typ
With R
SET = 5.1 k
Absolute Accuracy
2.5
% typ
With R
SET = 5.1 k
R
SET Range
3.0/11
k typ
I
CP Three-State Leakage
10
nA max
T
A = 85°C
Sink and Source Current Matching
2
% typ
0.5 V ≤ V
CP ≤ VP 0.5 V
I
CP vs. VCP
1.5
% typ
0.5 V ≤ V
CP ≤ VP 0.5 V
I
CP vs. Temperature
2
% typ
VCP = V
P/2
LOGIC INPUTS
V
IH, Input High Voltage
1.4
V min
V
IL, Input Low Voltage
0.6
V max
I
INH, IINL, Input Current
±1
A max
T
A = 25°C
C
IN, Input Capacitance
10
pF max
LOGIC OUTPUTS
V
OH, Output High Voltage
V
DD 0.4
V min
I
OH = 100 A
V
OL, Output Low Voltage
0.4
V max
I
OL = 500 A
POWER SUPPLIES
AV
DD
2.7/3.3
V min/max
DV
DD
AV
DD
V
P
AV
DD/5.5
V min/max
AV
DD ≤ VP ≤ 5.5 V
I
DD
4 (AI
DD + DIDD)
17
mA max
15 mA typ
I
P
2.0
mA max
T
A = 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor5
219
dBc/Hz typ
1 Operating temperature range (B version) is 40°C to +85°C.
2 AC coupling ensures AV
DD/2 bias. See Figure 13 for typical circuit.
3 Guaranteed by design. Characterized to ensure compliance.
4 T
A = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PNSYNTH = PNTOT 10logFPFD 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
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