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參數(shù)資料
| 型號： | ADF4007BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIVIDER/PLL SYNTHESZR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 7.5GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4007EBZ1-ND - BOARD EVALUATION FOR ADF4007EB1 |
Data Sheet
ADF4007
Rev. B | Page 13 of 16
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20-6) are rectangular.
The printed circuit board pad for these should be 0.1 mm longer
than the package land length and 0.05 mm wider than the package
land width. Center the land on the pad to ensure that the solder
joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. The printed circuit board should have
a clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern to ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.30 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
Connect the printed circuit board thermal pad to AGND.
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