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參數(shù)資料
| 型號(hào)： | ADF4007 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | High Frequency Divider/PLL Synthesizer |
| 中文描述： | 高分頻器/ PLL頻率合成器 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 390K |
| 代理商： | ADF4007 |
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ADF4007
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 5 of 16
15 MUXOUT
14 M1
13 M2
12 N1
11 N2
CPGND 1
AGND 2
AGND 3
RF
IN
B 4
RF
IN
A 5
2
A
D
A
D
R
I
D
D
1
S
1
P
1
D
1
D
PIN1
INDICATOR
ADF4007
TOPVIEW
0
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Function
1
CPGND
2, 3
AGND
4
RF
IN
B
Charge Pump Ground. The ground return path of the charge pump.
Analog Ground. The ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
Reference Input. A CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of 100 k.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Digital Ground.
These two bits set the N value. See Table 4.
These two bits set the status of MUXOUT and PFD polarity. See Table 5.
This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This pin should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the R
SET
pin is 0.66 V. The relationship between
I
CP
and
R
SET
is
5
25
=
5
6, 7
RF
IN
A
AV
DD
8
REF
IN
9, 10
11, 12
13, 14
15
16, 17
DGND
N2, N1
M2, M1
MUXOUT
DV
DD
18
V
P
19
R
SET
SET
MAX
CP
R
I
Therefore, if
R
SET
= 5.1 k, then
I
CP
= 5 mA.
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives the
external VCO.
20
CP
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| ADF4007BCPZ | 功能描述:IC DIVIDER/PLL SYNTHESZR 20LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4007BCPZ-RL | 功能描述:IC DIVIDER/PLL SYNTHESZR 20LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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