參數(shù)資料
型號: ADF4007
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: High Frequency Divider/PLL Synthesizer
中文描述: 高分頻器/ PLL頻率合成器
文件頁數(shù): 11/16頁
文件大?。?/td> 390K
代理商: ADF4007
ADF4007
APPLICATIONS
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
Figure 13 shows the ADF4007 being used with the
HMC358MS8G VCO from Hittite Microwave Corporation to
produce a fixed-frequency LO (local oscillator), which could be
used in satellite or CATV applications. In this case, the desired
LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREF
IN
and, in this case, is terminated in 50 . Many systems would
have either a TCXO or an OCXO driving the reference input
without any 50 termination. To bias the REF
IN
pin at AV
DD
/2,
ac coupling is used. The value of the coupling capacitor used
depends on the input frequency. The equivalent impedance at
the input frequency should be less than 10 . Given that the dc
input impedance at the REF
IN
pin is 100 k, less than 0.1% of
the signal is lost.
The charge pump output of the ADF4007 drives the loop filter.
In calculating the loop filter component values, a number of
items need to be considered. In this example, the loop filter was
designed so that the overall phase margin for the system is 45°.
Rev. 0 | Page 11 of 16
Other PLL system specifications are as follows:
K
D
= 5 mA
K
V
= 100 MHz/V
Loop Bandwidth = 300 kHz
F
PFD
= 106 MHz
N = 64
All these specifications are needed and used with the
ADIsimPLL to derive the loop filter component values shown in
Figure 13.
The circuit in Figure 13 gives a typical phase noise performance
of
100 dBc/Hz at 10 kHz offset from the carrier. Spurs are
heavily attenuated by the loop filter and are below
90 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50
matching between the VCO output, the RF output, and the RF
IN
terminal of the synthesizer.
ADF4007
N2
N1
M2
M1
100pF
100pF
100pF
CP
MUXOUT
G
G
G
5.6nF
51
18
22
NOTE
DECOUPLING CAPACITORS (0.1mF/10pF) ON AV
, DV
, AND V
OF THE ADF4007 AND ON
V
OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM
TO AID CLARITY.
R
SET
AV
DD
RF
IN
A
DV
DD
V
P
FREF
IN
VCO
100MHz/V
HMC358MS8G
R
SET
5.1k
6
17
18
8
20
15
19
9
3
2
10
0
RF
IN
B
5
4
11
12
13
14
GND
47nF
AV
DD
7
DV
DD
16
REF
IN
AV
DD
= 3.3V
1k
18k
V
CC
= 12V
V
CC
= 3.3V
1k
AD820
10pF
18
100pF
18
100pF
RF
OUT
LOGIC HI
LOGIC HI
LOGIC LO
LOGIC LO
Figure 13. 6.78 GHz Local Oscillator Using the ADF4007
相關(guān)PDF資料
PDF描述
ADF4007BCP High Frequency Divider/PLL Synthesizer
ADF4007BCP-REEL7 High Frequency Divider/PLL Synthesizer
ADF4106 PLL Frequency Synthesizer
ADF4106BCP PLL Frequency Synthesizer
ADF4106BRU PLL Frequency Synthesizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4007BCP 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:7.5 GHZ PLL SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL
ADF4007BCP-REEL 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R
ADF4007BCP-REEL7 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R
ADF4007BCPZ 功能描述:IC DIVIDER/PLL SYNTHESZR 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP(0.175",4.40mm 寬) 供應商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
ADF4007BCPZ-RL 功能描述:IC DIVIDER/PLL SYNTHESZR 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML,PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤,16-MLF? 供應商設(shè)備封裝:16-MLF?(3x3) 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND