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參數(shù)資料
| 型號： | ADF4001 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 200 MHz Clock Generator PLL |
| 中文描述： | 200 MHz的時鐘發(fā)生器，鎖相環(huán) |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | ADF4001 |
REV. 0
–2–
ADF4001–SPECIFICATIONS
1
CPGND = 0 V; R
SET
= 4.7 k
; T
A
= T
MIN
to T
MAX
unless otherwise noted; dBm referred to 50 )
Parameter
B Version
(AV
DD
= DV
DD
= 3 V 10%, 5 V 10%; AV
DD
≤
V
P
≤
6.0 V
; AGND = DGND =
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency
RF Input Sensitivity
See Figure 3 for Input Circuit
5/165
–10/0
MHz min/max
dBm min/max
RF CHARACTERISTICS (5 V)
RF Input Frequency
10/200
20/200
MHz min/max
MHz min/max
–5/0 dBm min/max
–10/0 dBm min/max
REFIN CHARACTERISTICS
REFIN Input Frequency
See Figure 2 for Input Circuit
For f < 5 MHz, Use DC-Coupled Square Wave
(0 to V
DD
)
AC-Coupled. When DC-Coupled:
0 to V
DD
max (CMOS-Compatible)
5/100
MHz min/max
REFIN Input Sensitivity
2
–5
dBm min
REFIN Input Capacitance
REFIN Input Current
10
±
100
pF max
μ
A max
PHASE DETECTOR
Phase Detector Frequency
3
55
MHz max
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
I
P
(AI
DD
+ DI
DD
)
ADF4001
I
P
Low Power Sleep Mode
Programmable: See Table V
With R
SET
= 4.7 k
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
μ
A typ
% typ
k
typ
nA typ
% typ
% typ
% typ
With R
SET
= 4.7 k
See Table V
0.5 V
≤
V
CP
≤
V
P
– 0.5
0.5 V
≤
V
CP
≤
V
P
– 0.5
V
CP
= V
P
/2
0.8
×
DV
DD
0.2
×
DV
DD
±
1
10
V min
V max
μ
A max
pF max
DV
DD
– 0.4
0.4
V min
V max
I
OH
= 500
μ
A
I
OL
= 500
μ
A
2.7/5.5
AV
DD
AV
DD
/6.0
V min/V max
V min/V max
AV
DD
≤
V
P
≤
6.0 V
5.5
0.4
1
mA max
mA max
μ
A typ
4.5 mA typical
T
A
= 25
°
C
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor
5
–161
–153
dBc/Hz typ
dBc/Hz typ
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCXO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
Phase Noise Performance
6
200 MHz Output
7
Spurious Signals
200 MHz Output
7
–99
dBc/Hz typ
–90/–95
dBc typ/dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40
°
C to +85
°
C.
2
AV
= DV
= 3 V; for AV
= DV
= 5 V, use CMOS-compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
T
A
= 25
°
C; AV
DD
= DV
DD
= 3 V; RF
IN
= 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 Evaluation Board and the HP8562E Spectrum Analyzer.
7
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
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