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參數(shù)資料
| 型號： | ADF4001 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 200 MHz Clock Generator PLL |
| 中文描述： | 200 MHz的時鐘發(fā)生器，鎖相環(huán) |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 190K |
| 代理商： | ADF4001 |
REV. 0
ADF4001
–
14
–
function. Figure 8 shows how the ADF4001 can be used to
handle all the possible combinations of input signal frequency
and sampling rate. The first ADF4001 is phase locked to a
VCO. The output of the VCO is also fed into the N divider of
the second ADF4001. This results in both ADF4001
’
s
being coherent with the REF
IN
. Since the REF
IN
comes from
the signal generator, the MUXOUT signal of the second
ADF4001 is coherent with the F
IN
frequency to the ADC. This is
used as F
S
, the sampling clock.
CP
RF
REF
IN
F
S
= (F
IN
N1)/(R1 N2)
A/D
CONVERTER
UNDER
TEST
ADF4001
ADF4001
SINE
OUTPUT
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
VCO
100MHz
LOOP
FILTER
RF
IN
RF
IN
MUXOUT
NC7S04
N2
N1
R1
F
IN
F
S
SAMPLING
CLOCK
A
IN
Figure 8. Coherent Clock Generator
TRI-BAND CLOCK GENERATION CIRCUIT
In multi-band applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz Master Clock. The low RF
Fmin spec and the ability to program R and N values as low as
1 makes the ADF4001 suitable for this. Other F
OUT
clock
frequencies can be realized using the formula:
F
REF
N
R
OUT
IN
=
÷
(
)
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic
“
1
”
is applied to the IN input.
The low-cost switch is available in both SOT-23 and micro
SO packages.
19.44MHz SYSTEM
CLOCK FOR WCDMA
19.2MHz SYSTEM
CLOCK FOR CDMA
13MHz SYSTEM
CLOCK FOR GSM
R2
1300
ADF4001
RF
IN
REF
IN
CP
RF
65
R3
CP
RF
ADF4001
REF
IN
RF
IN
R1
4
REF
IN
RF
IN
ADF4001
CP
RF
52MHz
MASTER
CLOCK
N2
486
LOOP
FILTER
VCXO
19.44MHz
N1
1
N3
24
VCXO
13MHz
VCXO
19.2MHz
LOOP
FILTER
LOOP
FILTER
Figure 9. Tri-Band System Clock Generation
FREF
IN
AGND
4
DGND
9
CPGND
3
ADF4001
RF
IN
A
RF
IN
B
100pF
100pF
51
AV
DD
V
DD
7
DV
DD
15
V
P
V
P
16
CE
10
1
2
R
SET
CP
POWER-DOWN CONTROL
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
6
5
10k
LOOP
FILTER
RF
OUT
18
18
18
100pF
ADG702
S
D
GND
V
DD
IN
V
CC
GND
VCO
OR
VCXO
Figure 10. Local Oscillator Shutdown Circuit
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| ADF4001BCP | 制造商:Rochester Electronics LLC 功能描述:CLOCK GENERATION PLL - Bulk 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4001BCPZ | 功能描述:IC CLOCK GEN PLL 200MHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4001BCPZ-RL | 功能描述:IC CLOCK GEN PLL 200MHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4001BCPZ-RL7 | 功能描述:IC CLOCK GEN PLL 200MHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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