![](http://datasheet.mmic.net.cn/310000/ADE7759ARSRL_datasheet_16240636/ADE7759ARSRL_29.png)
REV. 0
ADE7759
–29–
Address
Name
R/W
# of Bits
Default
Description
0Eh
ZXTOUT
R/W
12
FFFh
Zero Cross Timeout. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt
request line (
IRQ
) will be activated. The maximum timeout period is
0.15 second—see Zero Crossing Detection section.
Sag Line Cycle register. This 8-bit register specifies the number of
consecutive half-line cycles the signal on Channel 2 must be below
SAGLVL before the
SAG
output is activated—see Voltage Sag Detec-
tion section.
Interrupt Enable register. ADE7759 interrupts may be deactivated at
any time by setting the corresponding bit in this 8-bit Enable register
to Logic 0. The Status register will continue to register an interrupt
event even if disabled. However, the
IRQ
output will not be
activated—see Interrupts section.
Sag Voltage Level. An 8-bit write to this register determines at what
peak signal level on Channel 2 the
SAG
pin will become active. The
signal must remain low for the number of cycles specified in the
SAGCYC register before the
SAG
pin is activated—see Line Voltage
Sag Detection section.
Temperature register. This is an 8-bit register which contains the result of
the latest temperature conversion—see Temperature Measurement section.
Line Cycle Energy Accumulation Mode Half-Cycle register. This 14-
bit register is used during line cycle energy accumulation mode to set
the number of half-line cycles active energy is accumulated—see Line
Cycle Energy Accumulation Mode section.
Line Cycle Energy Accumulation Mode Active Energy register. This
40-bit register accumulates active energy during line cycle energy
accumulation mode. The number of half-line cycles is set by the
LINECYC register—see Line Cycle Energy Accumulation Mode section.
CF Frequency Divider Numerator register. The output frequency on
the CF pin is adjusted by writing to this 12-bit read/write register—see
Energy to Frequency Conversion section
.
Checksum register. This 6-bit read-only register is equal to the sum of
all the ones in the previous read—see Serial Read Operation section
.
Die Revision register. This 8-bit read-only register contains the revision
number of the silicon.
0Fh
SAGCYC
R/W
8
FFh
10h
IRQEN
R/W
8
40h
11h
SAGLVL
R/W
8
0h
12h
TEMP
R
8
0h
13h
LINECYC
R/W
14
3FFFh
14h
LENERGY
R
40
0h
15h
CFNUM
R/W
12
0h
1Eh
CHKSUM
R
6
0h
1Fh
DIEREV
R
8
01h
REGISTER DESCRIPTIONS
All ADE7759 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the Communications
register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section
of this data sheet.
Communications Register
The Communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7759 and the host
processor. All data transfer operations must begin with a write to the Communications register. The data written to the Communica-
tions register determines whether the next operation is a read or a write and which register is being accessed. Table V outlines the bit
designations for the Communications register.