參數(shù)資料
型號(hào)： ADE7758ARW
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： MS-013-AD, SOIC-24
文件頁(yè)數(shù)： 55/68頁(yè)
文件大?。?/td> 1584K
代理商： ADE7758ARW
ADE7758
INTERRUPT TIMING
The ADE7758 Serial Interface section should be reviewed first
before reviewing this interrupt timing section. As previously
described, when the IRQ output goes low, the MCU ISR must
read the interrupt status register in order to determine the
source of the interrupt. When reading the interrupt status
register contents, the IRQ output is set high on the last falling
edge of SCLK of the first byte transfer (read interrupt status
register command). The IRQ output is held high until the last
bit of the next 8-bit transfer is shifted out (interrupt status
register contents)—see Figure 87. If an interrupt is pending at
this time, the IRQ output goes low again. If no interrupt is
pending, the IRQ output remains high.
Rev. A | Page 55 of 68
ADE7758 SERIAL INTERFACE
The ADE7758 has a built-in SPI interface. The serial interface
of the ADE7758 is made of four signals: SCLK, DIN, DOUT,
and CS. The serial clock for a data transfer is applied at the
SCLK logic input. This logic input has a Schmitt trigger input
structure that allows slow rising (and falling) clock edges to be
used. All data transfer operations are synchronized to the serial
clock. Data is shifted into the ADE7758 at the DIN logic input
on the falling edge of SCLK. Data is shifted out of the ADE7758
at the DOUT logic output on a rising edge of SCLK. The CS
logic input is the chip select input. This input is used when
multiple devices share the serial bus. A falling edge on CS also
resets the serial interface and places the ADE7758 in commu-
nications mode. The CS input should be driven low for the
entire data transfer operation. Bringing CS high during a data
transfer operation aborts the transfer and place the serial bus in
a high impedance state. The CS logic input may be tied low if
the ADE7758 is the only device on the serial bus. However, with
CS tied low, all initiated data transfer operations must be fully
completed. The LSB of each register must be transferred
because there is no other way of bringing the ADE7758 back
into communications mode without resetting the entire device,
i.e., performing a software reset using Bit 6 of the OPMODE[7:0]
register, Address 0x13. The functionality of the ADE7758 is
accessible via several on-chip registers (see Figure 86). The
contents of these registers can be updated or read using the on-
chip serial interface. After a falling edge on CS, the ADE7758 is
placed in communications mode. In communications mode, the
ADE7758 expects the first communication to be a write to the
internal communications register. The data written to the
communications register contains the address and specifies the
next data transfer to be a read or a write command. Therefore,
all data transfer operations with the ADE7758, whether a read
or a write, must begin with a write to the communications
register.
0
COMMUNICATIONS
REGISTER
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
REGISTER NO. 1
REGISTER NO. 2
REGISTER NO. 3
REGISTER NO. n–1
REGISTER NO. n
REGISTER
ADDRESS
DECODE
DIN
DOUT
Figure 86. Addressing ADE7758 Registers via the Communications Register
0
IMASK
GLMASK RESET
INTERRUPT
FLAG
RESET (0x1A)
(BASED OISR ACTION
MCU
INTERRUPT
FLAG SET
PROGRAM
SEQUENCE
t
1
t
2
t
3
JTO
ISR
JTO
ISR
IRQ
Figure 87. ADE7758 Interrupt Management
STATUS REGISTER CONTENTS
0
SCLK
DIN
DOUT
READ STATUS REGISTER COMMAND
t
1
CS
0
0
0
1
0
0
0
DB15
DB8
DB7
DB0
1
t
9
t
11
t
12
IRQ
Figure 88. ADE7758 Interrupt Timing
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