參數(shù)資料
型號： ADE7753ARSRL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Active and Apparent Energy Metering IC with di/dt sensor interface
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： MO-150AE, SSOP-20
文件頁數(shù)： 33/38頁
文件大?。?/td> 449K
代理商： ADE7753ARSRL
ADE7753
–33–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Mode Register (09H)
T he ADE7753 functionality is configured by writing to the MODE register. T able VI below summarizes the functionality
of each bit in the MODE register .
T able VI : Mode Register
Bit
Location
Bit
Mnemonic
Default
Value
Description
0
1
2
3
4
D ISH PF
D ISL PF 2
D ISC F
D ISSA G
A SU SPE N D 0
0
0
1
1
T he HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.
T he LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.
T he Frequency output CF is disabled when this bit is set
T he line voltage Sag detection is disabled when this bit is set
By setting this bit to logic one, both ADE7753's A/D converters can be turned off. In
normal operation, this bit should be left at logic zero. All digital functionality can be
stopped by suspending the clock signal at CLK IN pin.
T he T emperature conversion starts when this bit is set to one. T his bit is automatically
reset to zero when the T emperature conversion is finished.
Software chip reset. A data transfer should not take place to the ADE7753 for at least 18μs
after a software reset.
Setting this bit to a logic one places the chip in line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
T hese bits are used to select the Waveform Register update rate
DT RT 1
D T R T 0
Update Rate
0
0
27.9kSPS (C L K IN/128)
0
1
14kSPS (C L K IN/256)
1
0
7kSPS (C L K IN/512)
1
1
3.5kSPS (C L K IN/1024)
T hese bits are used to select the source of the sampled data for the Waveform Register
WAV SE L 1,0
L ength Source
0
0
24 bits Active Power signal (output of LPF2)
0
1
Reserved
1
0
24 bits Channel 1
1
1
24 bits Channel 2
Writing a logic one to this bit will allow only positive power to be accumulated in the
ADE7753. T he default value of this bit is 0.
MODE REGISTER*
5
T E M PSE L
0
6
SW R ST
0
7
8
9
10
C Y C M OD E
D ISC H 1
D ISC H 2
SWAP
0
0
0
0
12, 11
D T R T 1,0
00
14, 13
WAV SE L 1,0 00
15
POA M
0
ADDR: 09H
0
1
2
3
4
5
6
7
0
0
1
1
0
0
0
0
(Positive Only AccumuPOAM
WAVSEL
(Wave form selection for sample mode)
00 = LPF2
01= Reserved
10 = CH1
11 = CH2
DISHPF
DISLPF2
(Disable LPF2 after multiplier)
DISCF
(Disable Frequency output CF)
DISSAG
(Disable SAG output)
*Register contents show power on defaults
(Suspend CH1&CH2 ADC’s)
STEMP
(Start temperature sensing)
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
DTRT
(Waveform samples output data rate)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4 kSPS (CLKIN/256)
10 = 7.2 kSPS (CLKIN/512)
11 = 3.6 kSPS (CLKIN/1024)
SWAP
(Swap CH1 & CH2 ADCs)
DISCH2
(Short the analog inputs on Channel 2)
DISCH1
(Short the analog inputs on Channel 1)
SWRST
(Software chip reset)
CYCMODE
(Line Cycle Energy Accumulation Mode)
ASUSPEND
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