參數(shù)資料
型號： ADE7169ASTF16-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： ANALOG CIRCUIT, PQFP64
封裝： MS-026BCD, LQFP-64
文件頁數(shù)： 84/140頁
文件大?。?/td> 1359K
代理商： ADE7169ASTF16-RL
ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 84 of 140
2
0xC2
WDS
0
WDS Watchdog status bit.
This bit is set to indicate that a watchdog timeout has occurred.
WDS is cleared by writing a zero or by an external hardware reset. A watchdog
reset will not clear WDS. The bit can therefore be used to distinguish between a
watchdog reset and a hardware reset from the RESET pin.
WDE Watchdog enable bit.
When set, enables the watchdog and clears its counter (e.g. 2 above). The
watchdog counter is subsequently cleared again whenever the WDE bit is set. If
the watchdog is not cleared within its selected timeout period it will generate a
system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is
disabled (and WDE cleared) by any of the following:
Write zero to WDE
Watchdog reset (WDIR = 0)
Hardware reset
PSM interrupt
LOCK interrupt.
WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a
double instruction sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR. This sequence is
necessary so that the WDCON SFR is protected from code execution upsets that
might unintentionally modify this SFR. Interrupts should be disabled during this
operation due to the consecutive instruction cycles.
e.g. Disable Watch dog
1 write to WDCON e.g. 2 Clear WDE bit
CLR EA
SETB WDWR
CLR WDE
SETB EA
1
0xC1
WDE
1
0
0xC0
WDWR
0
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in
Table
66
, is observed.
Table 66. Priority within Interrupt Level
Source
Priority
Description
IPSM
0 (Highest)
Power Supply Monitor Interrupt
IRTC
1
RTC Interval Timer interrupt
IADE
2
ADE Energy measurement interrupt
WDT
3
Watchdog Timer Overflow Interrupt
ITEMP
4
Temperature ADC interrupt
IE0
5
External Interrupt 0
TF0
6
Timer/Counter 0 Interrupt
IE1
7
External Interrupt 1
TF1
8
Timer/Counter 1 Interrupt
ISPI/I2CI
9
SPI/I
2
C Interrupt
RI/TI
10
UART Serial Port Interrupt
TF2/EXF2
11 (Lowest)
Timer/Counter 2 Interrupt
INTERRUPT FLAGS
The interrupt and status flags associated with the interrupt vectors are shown in Table 67 and Table 68. Most of the interrupts have flags
associated with them.
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