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| 型號(hào)： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁(yè)數(shù)： | 129/140頁(yè) |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
I
2
C COMPATIBLE INTERFACE
The ADE7169F16 supports a fully licensed
*
I
2
C interface. The
I
2
C interface is implemented as a full hardware master.
SDATA is the data I/O pin, and SCLK is the serial clock. These
two pins are shared with the MOSI and SCLK pins of the on-
chip SPI interface. Therefore, the user can enable only one
interface or the other on these pins at any given time. The SCPS
bit in the CFG SFR selects which peripheral is active.
The two pins used for data transfer, SDA and SCL are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
The transfer sequence of a I2C system consists of a master
device initiating a transfer by generating a START condition
while the bus is idle. The master transmits the address of the
slave device and the direction of the data transfer in the initial
address transfer. If the slave acknowledges then the data transfer
is initiated. This continues until the master issues a STOP
condition and the bus becomes idle.
I2C SFR REGISTER LIST
The I
2
C peripheral interface consists of five SFRs:
Rev. PrD | Page 129 of 140
SERIAL CLOCK GENERATION
The I
2
C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
Fast mode (256 kHz) or Standard mode (32 kHz).
The bit-rate is defined in the I2CMODE SFR as follow:
]
2
16
SCLDIV
core
SCL
f
f
×
=
SLAVE ADDRESSES
The I2CADR SFR contains the slave device ID. The LSB of this
register contains a read/write request. A write to this SFR will
start the I
2
C communication.
-
I2CMOD
-
SPI2CSTAT
-
I2CADR
-
SPI2CTx
-
SPI2CRx.
As the SPI and I2C serial interfaces share the same pins, I2CMODE, SPI2CSTAT, SPI2CTx and SPI2CRx SFRs are also shared with
SPIMODE1, SPI2CSTAT, SPITx and SPIRx SFRs respectively.
SFR Address
Name
R/W
Length
Default
Value
0
0
0
0
Description
0x9A
0x9B
0xE8
0xE9
0xEA
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
SPI2CSTAT
W
R
R/W
R/W
R/W
8
8
8
8
8
SPI Data out register
SPI Data in register
SPI configuration register
SPI configuration register
SPI/I2C Interrupt Status register
Table 128: SPI SFR register list
Table 129. I2C Mode Register SFR (I2CMOD, 0xE8)
Bit
Location
Addr.
7
0xEF
Bit
Bit
Name
I2CEN
Default
Value
Description
0
I2C enable bit
When this bit is set to logic one, the I2C interface is enabled. A write to the
I2CADR SFR will start a communication
I2C SCLK frequency
[1:0]
6-5
0xEE –
0xED
I2CR[1:0]
0
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