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參數(shù)資料
| 型號： | ADDI9023BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VERT DVR 12CH CCD 40CSPBGA |
| 標準包裝： | 2,500 |
| 類型： | CCD 垂直驅動器 |
| 應用： | 數(shù)碼相機 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-TFBGA, CSPBGA |
| 供應商設備封裝： | 40-CSPBGA (6x6) |
| 包裝： | 帶卷 (TR) |
ADDI9023
Data Sheet
Rev. 0 | Page 4 of 12
OUTPUT DRIVER SPECIFICATIONS
VH = 15 V, VM = 0 V, VL, VLL = 7.5 V, TA = 25°C.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
V1A TO V5
Delay Time, VL to VM and VM to VL
t
PLM, tPML
37
ns
Delay Time, VM to VH and VH to VM
t
PMH, tPHM
43
Rise Time, VL to VM
t
RLM
Load circuit: 20 Ω + 3 nF to GND
110
ns
Rise Time, VM to VH
t
RMH
Load circuit: 20 Ω + 3 nF to GND
240
ns
Fall Time, VM to VL
t
FML
Load circuit: 20 Ω + 3 nF to GND
180
ns
Fall Time, VH to VM
t
FHM
Load circuit: 20 Ω + 3 nF to GND
130
ns
Output Currents
V1A to V5 = 7.25 V
14
mA
V1A to V5 = 0.25 V
23
mA
V1A to V5 = +0.25 V
23
mA
V1A to V5 = +14.75 V
10
mA
On Resistance
R
ON
VH
23
35
Ω
VM
11
20
Ω
VL
17
25
Ω
V6 TO V9
Delay Time, VL to VM and VM to VL
t
PLM, tPML
37
ns
Rise Time, VL to VM
t
RLM
Load circuit: 20 Ω + 3 nF to GND
110
ns
Fall Time, VM to VL
t
FML
Load circuit: 20 Ω + 3 nF to GND
180
ns
Output Currents
V6 to V9 = 7.25 V
14
mA
V6 to V9 = 0.25 V
23
mA
On Resistance
R
ON
VM
11
20
Ω
VL
17
25
Ω
SUBCK OUTPUT
Delay Time, VLL to VH
t
PLH
47
ns
Delay Time, VH to VLL
t
PHL
47
ns
Rise Time, VLL to VH
t
RLH
Load circuit: 1 nF to GND
45
ns
Fall Time, VH to VLL
t
FHL
Load circuit: 1 nF to GND
45
ns
Output Currents
SUBCK = 7.25 V
23
mA
SUBCK = +14.75 V
22
mA
VLL On Resistance
R
ON
10
17
Ω
V-DRIVER
INPUT
tRLM, tRMH, tRLH
50%
10%
90%
tPLM, tPMH, tPLH
V-DRIVER
OUTPUT
10%
50%
90%
tFML, tFHM, tFHL
tPML, tPHM, tPHL
10693-
002
Figure 2. Definition of V-Driver Timing Specifications
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