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參數資料
| 型號： | ADDI9023BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VERT DVR 12CH CCD 40CSPBGA |
| 標準包裝： | 2,500 |
| 類型： | CCD 垂直驅動器 |
| 應用： | 數碼相機 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-TFBGA, CSPBGA |
| 供應商設備封裝： | 40-CSPBGA (6x6) |
| 包裝： | 帶卷 (TR) |
ADDI9023
Data Sheet
Rev. 0 | Page 10 of 12
APPLICATIONS INFORMATION
POWER-UP SEQUENCE
When the ADDI9023 is powered up, the following sequence is
recommended (refer to Figure 7 for each step). Note that VH is
powered on before VL but, depending on CCD restrictions, VH
and VL can also be powered on simultaneously.
1. Turn on the VDD power supply, either 1.8 V or 3.3 V. After
VDD settles, the logic inputs from the timing generator (XV,
XSG, XSUBCK) can become active. Keep VDREN low during
this time.
2. Turn on the VH power supply, typically +12 V to +15 V.
3. Turn on the VL/VLL power supply, typically 6 V to 9 V.
4. Take the VDREN pin high to enable the V-driver outputs.
VDREN must remain high throughout normal vertical
timing operation.
POWER-DOWN SEQUENCE
When the ADDI9023 is powered down, reverse the procedure
shown in Figure 7.
1. Take the VDREN pin low to disable the V-driver outputs.
2. Turn off the VL/VLL and VH power supplies.
3. Turn off the VDD power supply.
0V
VH SUPPLY
VL, VLL SUPPLY
1
2
0V
VM
VH
VL/VLL (SUBCK ONLY)
XV, XSG,
XSUBCK
(INPUT)
VM
V-DRIVER OUTPUTS ACTIVE
WHEN VDREN IS HIGH
VDD
V1A TO V9
(OUTPUT)
VDREN
POWER
SUPPLIES
0V
VDD
4
VDD
3
DON’T CARE
10693-
008
Figure 7. Recommended Power-Up Sequence
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