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參數(shù)資料
| 型號： | ADCMP567BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP DUAL ULTRA-FAST 32LFCSP |
| 標準包裝： | 1 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 補充型，差分，開路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 24µA @ 5V |
| 電流 - 輸出（標準）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 20mA，95mA，18mA |
| CMRR, PSRR（標準）： | 69dB CMRR |
| 傳輸延遲（最大）： | 0.3ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP567BCPZ-ND - BOARD EVALUATION ADCMP567BCP |
ADCMP567
Rev. 0 | Page 10 of 16
as the variation in propagation delay as the input overdrive
conditions are changed (Figure 4). For the ADCMP567,
overdrive dispersion is typically 35 ps as the overdrive is
changed from 100 mV to 1 V. This specification applies for
both positive and negative overdrive since the ADCMP567 has
equal delays for positive and negative going inputs.
The 35 ps propagation delay overdrive dispersion of the
ADCMP567 offers considerable improvement of the 100 ps
dispersion of other similar series comparators.
Q OUTPUT
INPUT VOLTAGE
1.5V OVERDRIVE
20mV OVERDRIVE
DISPERSION
VREF ± VOS
03633-0-004
Figure 4. Propagation Delay Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a
noisy environment or where it is not desirable for the com-
parator to toggle between states when the input signal is at the
switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 5. If the input voltage
approaches the threshold from the negative direction, the
comparator will switch from a 0 to a 1 when the input crosses
+VH/2. The new switching threshold becomes VH/2. The
comparator will remain in a 1 state until the threshold VH/2 is
crossed coming from the positive direction. In this manner,
noise centered on 0 V input will not cause the comparator to
switch states unless it exceeds the region bounded by ±VH/2.
Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 9). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.
Another method to implement hysteresis is generated by
introducing a differential voltage between LATCH ENABLE
and LATCH ENABLE. inputs (Figure 10). Hysteresis generated
in this manner is independent of output swing and is symmetri-
cal around zero. The variation of hysteresis with input voltage is
shown in Figure 6.
OUTPUT
INPUT
0
1
0V
–VH
2
+VH
2
03633-0-005
Figure 5. Comparator Hysteresis Transfer Function
LATCH = LE – LEB (mV)
H
YSTER
ESIS
(
m
V)
–25
0
10
20
30
40
50
60
–15
–20
–10
–5
0
5
03632-0-006
Figure 6. Comparator Hysteresis Transfer Function
Using Latch Enable Input
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 5 V/s
or faster to ensure a clean output transition. If slew rates less
than 5 V/s are used, then hysteresis should be added to reduce
the oscillation.
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