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參數(shù)資料
| 型號(hào)： | ADCMP567BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP DUAL ULTRA-FAST 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 補(bǔ)充型，差分，開(kāi)路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 24µA @ 5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 20mA，95mA，18mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 69dB CMRR |
| 傳輸延遲（最大）： | 0.3ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán)，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP567BCPZ-ND - BOARD EVALUATION ADCMP567BCP |
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ADCMP567
Rev. 0 | Page 7 of 16
Pin No.
Mnemonic
Function
22
VEE
Negative Supply Terminal
23
NC
No Connect. Leave pin unconnected.
24
VEE
Negative Supply Terminal
25
VDD
Logic Supply Terminal
26
QA
One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
27
QA
One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
28
VDD
Logic Supply Terminal
29
NC
No Connect. Leave pin unconnected.
30
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
31
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA.
32
GND
Analog Ground
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