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參數(shù)資料
| 型號(hào)： | ADCMP562BRQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Dual High Speed PECL Comparators |
| 中文描述： | COMPARATOR, 10000 uV OFFSET-MAX, PDSO20 |
| 封裝： | MO-137AD, QSOP-20 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 335K |
| 代理商： | ADCMP562BRQ |
ADCMP561/ADCMP562
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. A | Page 6 of 16
0
ADCMP561
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
QA
V
DD
V
EE
LEA
LEA
–INB
+INB
QB
QB
GND
V
CC
LEB
LEB
0
ADCMP562
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
QA
V
DD
V
EE
LEA
LEA
V
DD
+INA
HYSA
–INB
QB
QB
GND
V
CC
LEB
LEB
V
DD
+INB
HYSB
Figure 4. ADCMP561 16-Lead QSOP Pin Configuration
Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP561
ADCMP562
1
1
2
Mnemonic
V
DD
QA
Function
Logic Supply Terminal.
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
Logic Supply Terminal.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In the latch mode (logic low), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting
A input must be driven in conjunction with the inverting A input.
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting
B input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
Positive Supply Terminal.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to placing the comparator in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to placing the comparator in the latch mode. LEB must be
driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.
2
3
QA
3
4
4
5
V
DD
LEA
5
6
LEA
6
7
7
8
V
EE
INA
8
9
+INA
9
10
11
12
HYSA
HYSB
+INB
10
13
INB
11
12
14
15
V
CC
LEB
13
16
LEB
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