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參數(shù)資料
| 型號(hào)： | ADCLK954/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL CLK BUFF ADCLK954 |
| 設(shè)計(jì)資源： | ADCLK954/950 Brd Schematic ADCLK954 BOM ADCLK954 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SIGe |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCLK954 |
| 主要屬性： | 2 輸入，12 輸出 |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
ADCLK954
Rev. B | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. EPAD MUST BE SOLDERED TO VEE POWER PLANE.
1
IN_SEL
2
CLK0
3
CLK0
4
VREF0
5
VT0
6
CLK1
7
CLK1
8
VT1
9
VREF1
10
VEE
23 Q7
24 Q6
25 Q6
26 Q5
27 Q5
28 Q4
29 Q4
30 VCC
22 Q7
21 VCC
11
V
C
12
Q
11
13
Q
11
15
Q
10
17
Q
9
16
Q
9
18
Q
8
19
Q
8
20
V
C
14
Q
10
33
Q
3
34
Q
2
35
Q
2
36
Q
1
37
Q
1
38
Q
0
39
Q
0
40
V
C
32
Q
3
31
V
C
TOP VIEW
(Not to Scale)
ADCLK954
07
96
8-
00
2
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IN_SEL
Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.
2
CLK0
Differential Input (Positive) 0.
3
CLK0
Differential Input (Negative) 0.
4
VREF0
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.
5
VT0
Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.
6
CLK1
Differential Input (Positive) 1.
7
CLK1
Differential Input (Negative) 1.
8
VT1
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.
9
VREF1
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.
10
VEE
Negative Supply Pin.
11, 20, 21,
30, 31, 40
VCC
Positive Supply Pin.
12, 13
Q11, Q11
Differential LVPECL Outputs.
14, 15
Q10, Q10
Differential LVPECL Outputs.
16, 17
Q9, Q9
Differential LVPECL Outputs.
18, 19
Q8, Q8
Differential LVPECL Outputs.
22, 23
Q7, Q7
Differential LVPECL Outputs.
24, 25
Q6, Q6
Differential LVPECL Outputs.
26, 27
Q5, Q5
Differential LVPECL Outputs.
28, 29
Q4, Q4
Differential LVPECL Outputs.
32, 33
Q3, Q3
Differential LVPECL Outputs.
34, 35
Q2, Q2
Differential LVPECL Outputs.
36, 37
Q1, Q1
Differential LVPECL Outputs.
38, 39
Q0, Q0
Differential LVPECL Outputs.
EPAD
Exposed pad (EPAD) must be connected to VEE.
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