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參數(shù)資料
| 型號： | ADCLK914BCPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA BUFF DVR 1:1 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | SIGe |
| 類型： | 緩沖器/驅(qū)動器，數(shù)據(jù) |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，LVDS，LVPECL，LVTTL |
| 輸出： | HVDS |
| 頻率 - 最大： | 7.5GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 托盤 - 晶粒 |
ADCLK914
Rev. A | Page 9 of 12
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCLK914 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each power supply pin to ground. In addition, place
multiple high quality 0.001 μF bypass capacitors as close as
possible to each VEE and VCC supply pin and connect these cap-
acitors to the GND plane with redundant vias. Carefully select
high frequency bypass capacitors for minimum inductance and
ESR. To maximize the effectiveness of the bypass capacitors at
high frequencies, strictly avoid parasitic layout inductance.
Slew currents may also appear at the VDD and VSS pins of the
device being driven by the ADCLK914.
HVDS OUTPUT STAGE
The ADCLK914 has been developed to provide a bipolar interface
to any CMOS device that requires extremely low jitter, high
amplitude clocks. It is intended to be placed as close as possible
to the receiving device and allows the rest of the clock distribu-
tion to run at standard CML or PECL levels.
Interconnects must be short and very carefully designed
because the single terminated design provides much less
margin for error than lower voltage, double terminated
transmission techniques.
06
56
1-
0
15
VEE
Q
40mA
VEE
7mA
VEE
7mA
Figure 14. Simplified Schematic Diagram
of the ADCLK914 HVDS Output Stage
INTERFACING TO HIGH SPEED DACs
The ADCLK914 is designed to drive high amplitude, low jitter
clock signals into high speed, multi-GSPS DACs. The ADCLK914
should be placed as close as possible to the clock input of the
DAC so that the high slew rate and high amplitude clock signal
that these devices require do not cause routing difficulties,
generate EMI, or become degraded by dielectric and other
losses. The ADCLK914, in turn, may be driven directly by
standard or low swing PECL, CML, CMOS, or LVTTL sources,
or by LVDS with simple ac coupling, as illustrated in Figure 15
through Figure 19.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed circuit, proper design and layout tech-
niques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances, as well as other layout issues, can severely limit
performance and can cause oscillation. Discontinuities along
input and output transmission lines can also severely limit the
specified jitter performance by reducing the effective input
slew rate.
Input and output matching have a significant impact on
performance. The ADCLK914 buffer provides internal 50 Ω
termination resistors for both D and D inputs. The return side
can be connected to the reference pin provided or to a current
sink at VCC 2 V for use with differential PECL, or to VCC for
direct coupled CML. The VREF pin should be left floating any
time that it is not used to minimize power consumption.
Note that the ADCLK914 VREF source is current-limited to resist
damage from momentary shorts to VEE or VCC and from capacitor
charging currents; for this reason, the VREF source cannot be
used as a PECL termination supply.
Carefully bypass the termination potential using ceramic capa-
citors to prevent undesired aberrations on the input signal due
to parasitic inductance in the termination return path. If the
inputs are directly coupled to a source, care must be taken to
ensure that the pins remain within the rated input differential
and common-mode ranges.
If the return is floated, the device exhibits 100 Ω cross-term-
ination, but the source must then control the common-mode
voltage and supply the input bias currents.
ESD/clamp diodes between the input pins prevent the appli-
cation of excessive offsets to the input transistors. ESD diodes
are not optimized for best ac performance. If a clamp is needed,
it is recommended that appropriate external diodes be used.
RANDOM JITTER
The ADCLK914 buffer has been specifically designed to
minimize random jitter over a wide input range. Provided
that sufficient voltage swing is present, random jitter is affected
most by the slew rate of the input signal. Whenever possible,
clamp excessively large input signals with fast Schottky diodes
because attenuators reduce the slew rate. Input signal runs of
more than a few centimeters should be over low loss dielectrics
or cables with good high frequency characteristics.
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