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參數(shù)資料
| 型號： | ADC912AFS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 237K |
| 代理商： | ADC912AFS |
REV. B
ADC912A
–8–
CIRCUIT CHARACTERISTICS
The characteristic curves provide more complete static and
dynamic accuracy information necessary for repetitive sampling
applications often used in DSP processing. One of the impor-
tant characteristic curves provided displays integral nonlinearity
error (INL) versus output code with a typical value of
±
1/4 LSB.
Another very important characteristic associated with INL is the
transition noise shown in the transition noise cross plot. The
ADC912A offers extremely small,
±
1/6 LSB, transition noise
which maintains the system signal-to-noise ratio in DSP processing
applications. Code repetition plots show the precision internal
comparator of the ADC912A making the same decision every
time for dc input voltages. Code repetition along with no miss-
ing codes assures proper performance when the ADC912A is
used in servo-control systems.
CONVERTER OPERATION DETAILS
The
CS
,
RD
, and HBEN digital inputs control the start of
conversion. A high-to-low on both
CS
and
RD
initiate a conver-
sion sequence. The HBEN high-byte-enable input must be low
or coincident with the read
RD
input edge. The start of conver-
sion resets the internal successive approximation register (SAR)
and enables the three-state outputs. See Figure 11. The busy
line is active low during the conversion process.
SAR
12-BIT LATCH
–
+
5k
2.5k
A
IN
V
REFIN
AGND
0 TO
–
V
REF
COMPARATOR
12
0V TO 10V
Figure 11. Simplified Analog Input Circuitry of ADC912A
During conversion, the SAR sequences the internal voltage
output DAC from the most significant bit (MSB) to the least
significant bit (LSB). The analog input connects to the
comparator via a 5 k
resistor. The DAC, which has a 2.5 k
output resistance, connects to the same comparator input.
The comparator, performing a zero crossing detection, tests the
addition of successively weighted bits from the DAC output
versus the analog input signal. The MSB decision occurs 200 ns
after the second positive edge of the CLK IN following conver-
sion initiation. The remaining 11-bit trials occur after the next
11 positive CLK IN edges. Once a conversion cycle is started it
cannot be stopped or restarted, without upsetting the remaining
bit decisions. Every conversion cycle must have 13 negative and
positive CLK IN edges. At the end of conversion the compara-
tor input voltage is zero. The SAR contains the 12-bit data
word representing the analog input voltage. The BUSY line
returns to logic high, signaling end of conversion. The SAR
transfers the new data to the 12-bit latch.
SYNCHRONIZING START CONVERSION
Aligning the negative edge of
RD
with the rising edge of CLK
IN provides synchronization of the internal start conversion
signal to other system devices for sampling applications.
When the negative edge of
RD
is aligned with the positive edge
of CLK IN, the conversion will take 10.4 microseconds. The
minimum setup time between the negative edge of CLK IN and
the negative edge of
RD
is 180 ns. Without synchronization the
conversion time will vary from 12.5 to 13.5 clock cycles. See
Figure 12.
CLK IN
CS RD
,
BUSY
180ns MIN
DB
11
(MSB)
DB
10
DB
9
DB
0
BIT DECISION
MADE
Figure 12. External Clock Input Synchronization
POWER ON INITIALIZATION
During system power-up the ADC912A comes up in a random
state. Once the clock is operating or an external clock is applied,
the first valid conversion begins with the application of a high-
to-low transition on both
CS
and
RD
. The next 13 negative
clock edges complete the first conversion, producing valid data
at the digital outputs. This is important in battery-operated
systems where power supplies are shut down between measure-
ment times.
DRIVING THE ANALOG INPUT
During conversion, the internal DAC output current modulates
the analog input current at the CLK IN frequency of 1.25 MHz.
The analog input to the ADC912A must not change during the
conversion process. This requires an external buffer with low
output impedance at 1.25 MHz. Suitable devices meeting this
requirement include the OP27, OP42, and the SMP-11.
CLK
OUT
C2
CLK
IN
ADC912A
INTERNAL
CLOCK
1M
*
*
CRYSTAL OR CERAMIC RESONATOR
C1
Figure 13. ADC912A Simplified Internal Clock Circuit
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