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參數(shù)資料
| 型號： | ADC912AFS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 237K |
| 代理商： | ADC912AFS |
REV. B
ADC912A
–3–
t
CONV
t
6
t
7
DATA
OUTPUTS
READ
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
t
1
t
2
t
3
t
5
t
1
t
10
OLD DATA
DB
11
–
DB
0
NEW DATA
DB
11
–
DB
0
CS
RD
BUSY
DATA
Figure 5. Parallel Read Timing Diagram, Slow-Memory
Mode (HBEN = LOW)
CS
RD
BUSY
DATA
HBEN
DATA
OUTPUTS
FIRST READ
SECOND READ
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
LOW
LOW
LOW
LOW
DB
11
DB
10
DB
9
DB
8
t
8
t
1
t
2
t
3
t
CONV
t
6
t
7
t
5
t
9
t
8
t
1
t
10
t
3
t
7
t
5
t
9
t
4
NEW DATA
DB
7
–
DB
0
NEW DATA
DB
11
–
DB
8
OLD DATA
DB
7
–
DB
0
Figure 6. Two-Byte Read Timing Diagram, Slow-Memory
Mode
TIMING CHARACTERISTICS
1, 2
(V
DD
= +5 V 5%, V
SS
= –11.4 V to –15.75 V, V
REFIN
= –5 V, Analog Input 0 V to 10 V;
External f
CLK
= 1.25 MHz; –40 C to +85 C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CS
to
RD
Setup Time
RD
to
BUSY
Propagation Delay
Data Access Time after READ
Read Pulsewidth
CS
to
RD
Hold Time
New Data Valid after
BUSY
Bus Disconnect Time
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
Delay between Successive Read Operations
t
1
t
2
t
33
t
43
t
5
t
63
t
7
t
8
t
9
t
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
125
C
L
= 100 pF
65
90
0
C
L
= 100 pF
–30
60
0
90
20
20
20
350
250
NOTES
1
Guaranteed by design.
2
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
t
3
, t
4
, and t
6
are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.
4
t
7
is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
TIMING DIAGRAMS
CS
RD
BUSY
DATA
t
1
t
2
t
3
t
7
t
3
t
7
t
CONV
t
5
t
1
t
2
t
CONV
t
5
t
4
NEW DATA
DB
11
–
DB
0
OLD DATA
DB
11
–
DB
0
DATA
OUTPUTS
FIRST READ
(OLD DATA)
SEREADDB
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
t
4
Figure 7. Parallel Read Timing Diagram, ROM Mode
(HBEN = LOW)
DATA
OUTPUTS
FIRST READ
(OLD DATA)
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
SECOND READ
LOW
LOW
LOW
LOW
DB
11
DB
10
DB
9
DB
8
THIRD READ
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
t
8
t
1
t
2
t
3
t
7
t
4
t
9
t
5
t
8
t
1
t
3
t
4
t
9
t
10
t
3
t
7
t
2
t
4
t
1
t
5
t
8
t
9
t
7
t
5
CS
RD
BUSY
DATA
HBEN
NEW DATA
DB
7
–
DB
0
NEW DATA
DB
11
–
DB
8
OLD DATA
DB
7
–
DB
0
t
CONV
Figure 8. Two-Byte Read Timing Diagram, ROM Mode
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