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參數(shù)資料
| 型號： | ADC774 |
| 英文描述： | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 微處理器兼容模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 87K |
| 代理商： | ADC774 |
6
ADC774
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the A
O
input, which is latched upon receipt of a conver-
sion start transition (described below). If A
O
is latched high,
the conversion continues for 8 bits. The full 12-bit conver-
sion will occur if A
O
is low. If all 12 bits are read following
an 8-bit conversion, the 3 LSBs (DB0–DB2) will be low
(logic 0) and DB3 will be high (logic 1). A
O
is latched
because it is also involved in enabling the output buffers. No
other control inputs are latched.
CE
t
SSR
t
SRR
t
HRR
t
HS
t
HD
High-Z
CS
R/C
STS
DB11–
DB0
t
HSR
A
O
t
HAR
t
SAR
Data Valid
t
HL
t
DD
FIGURE 4. Read Cycle Timing.
FIGURE 3. Conversion Cycle Timing.
Figure 1 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs
go to the high-impedance state in response to the falling
edge of R/C and are enabled for external access of the data
after completion of the conversion. Figure 2 illustrates the
timing when conversion is initiated by a positive R/C pulse.
In this mode the output data from the previous conversion is
enabled during the positive portion of R/C. A new conver-
sion is started on the falling edge of R/C, and the three-state
outputs return to the high-impedance state until the next
occurrence of a high R/C pulse. Timing specifications for
stand-alone operation are listed in Table III.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
C
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
A
O
to CE setup
A
valid during CE high
Conversion time
12-bit cycle at 25
°
C
0 to +75
°
C
–55
°
C to +125
°
C
8-bit cycle at 25
°
C
0 to +75
°
C
–55
°
to +125
°
C
60
30
20
20
0
20
200
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
50
50
0
50
20
7.5
8.5
9.0
9.5
5.3
5.6
6
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
5
Read Mode
t
DD
t
HD
t
HL
t
SSR
t
SAR
t
HSR
t
HRR
t
HAR
t
HS
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
CS valid after CE low
R/C high after CE low
A
valid after CE low
STS delay after data valid
75
35
100
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
150
50
0
0
0
50
150
375
TABLE IV. Timing Specifications.
CE
t
HEC
t
SSC
t
SRC
t
HSC
t
HRC
t
HAC
t
SAC
t
DSC
t
C
High Impedance
CS
R/C
STS
DB11–
DB0
A
O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC774JH | 制造商:BURR-BROWN 功能描述: 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| ADC774JH-BI | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC774JP | 制造商:BURR-BROWN 功能描述: 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 |
| ADC774JP-BI | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
| ADC774KH | 制造商:BB 制造商全稱:BB 功能描述:Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER |
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