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5
ADC774
CONTROLLING THE ADC774
This is an abridged data sheet. For Discussion of Specifica-
tions, Installation, Calibration refer to ADC574A data sheet
or order PDS-835.
The Burr-Brown ADC774 can be easily interfaced to most
microprocessor systems and other digital systems. The
microprocessor may take full control of each conversion, or
the converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion, and
reading the output data when ready—choosing either 12 bits
all at once, or 8 bits followed by 4 bits in a left-justified
format. The five control inputs (12/8, CS, A
O
, R/C, and CE)
are all TTL-/CMOS-compatible. The functions of the con-
trol inputs are described in Table I. The control function
truth table is listed in Table II.
Read footnote 5 to the Electrical Specifications table if
using ADC774 to replace the HI-774.
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is ac-
complished by a single control line connected to R/C. In this
mode CS and A
O
are connected to digital common and CE
and 12/8 are connected to V
LOGIC
(+5V). The output data
are presented as 12-bit words. The stand-alone mode is used
in systems containing dedicated input ports which do not
require full bus interface capability.
PIN
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
Chip Enable
(active high)
Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
CS (Pin 3)
Chip Select
(active low)
Must be low (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate
a conversion.
R/C (Pin 5)
Read/Convert
(“1” = read)
(“0” = convert)
Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a
conversion. Must be high (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
A
O
(Pin 4)
Byte Address
Short Cycle
In the start-convert mode, A
selects 8-bit (A
= “1”) or 12-bit (A
= “0”) conversion mode. When reading
output data in two 8-bit bytes, A
O
= “0” accesses 8 MSBs (high byte) and A
O
= “1” accesses 4 LSBs and
trailing “0s” (low byte).
12/8 (Pin 2)
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
MSBs or LSBs as determined by the A
O
line.
TABLE I. ADC774 Control Line Functions.
CE
CS
R/C
12/8
A
O
OPERATION
0
X
X
1
0
0
X
X
0
0
0
0
X
X
X
X
X
X
X
X
1
0
0
X
X
0
1
0
1
0
1
X
0
1
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus 4
trailing zeros
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
TABLE II. Control Input Truth Table.
SYMBOL PARAMETER
MIN
TYP
MAX
UNITS
t
HRL
t
DS
t
HDR
t
HS
t
HRH
t
DDR
Data Access Time
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
STS Delay After Data Valid
High R/C Pulse Width
50
ns
ns
ns
ns
ns
ns
200
25
150
375
150
150
TABLE III. Stand-Alone Mode Timing.
Conversion is initiated by a high-to-low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In either case the R/C pulse
must remain low for a minimum of 50ns.
FIGURE 2. R/C Pulse High—Outputs Enabled Only While
R/C Is High.
R/C
STS
DB11–
DB0
Data Valid
High-Z State
t
HRH
t
DS
t
DDR
High-Z
t
C
t
HDR
FIGURE 1. R/C Pulse Low—Outputs Enabled After Con-
version.
R/C
STS
DB11–DB0
Data Valid
Data Valid
High-Z State
t
HRL
t
DS
t
HDR
t
HS
t
C