參數(shù)資料
型號: ADC1412D080HN
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual 14-bit ADC 80 Msps CMOS or LVDS DDR digital outputs
封裝: ADC1412D080HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1412D080HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 29/43頁
文件大?。?/td> 1347K
代理商: ADC1412D080HN
ADC1412D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 4 March 2011
29 of 43
NXP Semiconductors
ADC1412D series
Dual 14-bit ADC: CMOS or LVDS DDR digital outputs
11.5.6
Test patterns
For test purposes, the ADC1412D can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see
Table 27
). A custom test pattern
can be defined by the user (TESTPAT_USER[13:6]; see
Table 28
and
TESTPAT_USER[5:0]; see
Table 29
) and is selected when TESTPAT_SEL[2:0] = 101.
The selected test pattern is transmitted regardless of the analog input.
11.5.7
Output codes versus input voltage
Table 16.
V
INAP
V
INAM
/
V
INBP
V
INBM
<
1
1
0.9998779
0.9997559
0.9996338
0.9995117
....
0.0002441
0.0001221
+0
11.6 Serial Peripheral Interface (SPI)
11.6.1
Register description
The ADC1412D serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see
Table 18
).
Output codes
Offset binary
Two’s complement
OTRA/OTRB
pin
1
0
0
0
0
0
0
0
0
0
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
00 0000 0000 0011
00 0000 0000 0100
....
01 1111 1111 1110
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
....
11 1111 1111 1011
11 1111 1111 1100
11 1111 1111 1101
11 1111 1111 1110
11 1111 1111 1111
11 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
10 0000 0000 0011
10 0000 0000 0100
....
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
....
01 1111 1111 1011
01 1111 1111 1100
01 1111 1111 1101
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
+0.0001221
+0.0002441
....
+0.9995117
+0.9996338
+0.9997559
+0.9998779
+1
> +1
0
0
0
0
0
0
0
0
1
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