- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382830 > ADC1213S065HN (NXP Semiconductors N.V.) Single 12 bits ADC; 65 Msps; serial JESD204A PDF資料下載
參數(shù)資料
| 型號(hào)： | ADC1213S065HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 12 bits ADC; 65 Msps; serial JESD204A |
| 封裝： | ADC1213S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1213S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁(yè)數(shù)： | 32/39頁(yè) |
| 文件大?。?/td> | 719K |
| 代理商： | ADC1213S065HN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)
ADC1213S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
32 of 39
NXP Semiconductors
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
Table 41.
Default values are highlighted.
Bit
Symbol
7 to 1
-
0
S
Cfg_9_S (address 0828h)
Access
-
R/W
Value
0000000
0
Description
not used
defines number of samples per converter per frame cycle
Table 42.
Default values are highlighted.
Bit
Symbol
7
HD
6 to 2
-
1 to 0
CF[1:0]
Cfg_10_HD_CF (address 0829h)
Access
R/W
-
R/W
Value
*
00000
00
Description
defines high density format
not used
defines number of control words per frame clock cycle per link.
Table 43.
Default values are highlighted.
Bit
Symbol
7 to 5
-
4 to 0
LID[4:0]
Cfg_02_2_LID (address 082Dh)
Access
-
R/W
Value
000
11100
Description
not used
defines lane identification number
Table 44.
Default values are highlighted.
Bit
Symbol
7 to 0
FCHK[7:0]
Cfg02_13_FCHK (address 084Dh)
Access
R
Value
********
Description
defines the checksum value for lane
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 45.
Default values are highlighted.
Bit
Symbol
7
-
6
SCR_IN_MODE
Lane_0_Ctrl (address 0871h)
Access
-
R/W
Value
0
Description
not used
defines the input type for scrambler and 8-bit/10-bit units:
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
defines output type of lane output unit:
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0
0)
toggle mode: lane output is toggling between 0
0 and 0
1
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
not used
0
(reset)
1
5 to 4
LANE_MODE[1:0]
R/W
00
(reset)
01
10
11
3
-
-
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC1213S065HN | Single 12 bits ADC; 65 Msps; serial JESD204A |
| ADC1213S080HN | Single 12 bits ADC; 80 Msps; serial JESD204A |
| ADC1213S105HN | Single 12 bits ADC; 105 Msps; serial JESD204A |
| ADC1213S125HN | Single 12 bits ADC; 125Msps; serial JESD204A |
| ADC1410S065HN | Single 14-bit ADC 65 Msps CMOS or LVDS DDR digital outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1213S065HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 65MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1213S065HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Bulk |
| ADC1213S065HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
| ADC1213S080C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。