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參數(shù)資料
| 型號： | ADC1113S125HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 11 bits ADC; 125Msps; serial JESD204A |
| 封裝： | ADC1113S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1113S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁數(shù)： | 21/38頁 |
| 文件大小： | 648K |
| 代理商： | ADC1113S125HN |
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ADC1113S125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 15 March 2011
28 of 38
NXP Semiconductors
ADC1113S125
Single 11-bit ADC; serial JESD204A interface
11.6.4 JESD204A digital control registers
Table 24.
Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_2[10:3]
R/W
00000000 custom digital test pattern (bit 10 to 3)
Table 25.
Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
TESTPAT_3[2:0]
R/W
000
custom digital test pattern (bit 2 to 0)
4 to 0
-
00000
not used
Table 26.
Ser_Status (address 0801h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
RXSYNC_ERROR
R
0
set to 1 when a synchronization error occurs
6 to 4
RESERVED[2:0]
-
001
reserved
3 to 2
-
00
not used
1POR_TST
R
0
power-on-reset
0
RESERVED
-
0
reserved
Table 27.
Ser_Reset (address 0802h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7SW_RST
R/W
0
initiates a software reset of the JESD204A unit
6 to 4
-
000
not used
3FSM_SW_RST
R/W
0
initiates a software reset of the internal state machine of
JESD204A unit
2 to 0
-
000
not used
Table 28.
Ser_Control1 (address 0805h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
0
not used
6
RESERVED
-
1
reserved
5
SYNC_POL
R/W
defines the synchronization signal polarity:
0
synchronization signal is active LOW
1
synchronization signal is active HIGH
4
SYNC_SINGLE_ENDED R/W
defines the input mode of the synchronization signal:
0
synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
3
-
1
not used
2
REV_SCR
-
LSBs are swapped with MSBs at the scrambler input:
0
disable
1
enable
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相關代理商/技術參數(shù) |
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|---|---|
| ADC1113S125HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 11BT ADC 125MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1113S125HN/C1,551 | 制造商:NXP Semiconductors 功能描述:Bulk 制造商:NXP Semiconductors 功能描述:0 |
| ADC1113S125HN-C1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1113S125HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
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