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參數(shù)資料
| 型號(hào)： | ADAV803ASTZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 32/56頁(yè) |
| 文件大小： | 906K |
| 代理商： | ADAV803ASTZ-REEL |
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ADAV803
REGISTER DESCRIPTIONS
Table
ADDRESS = 0000000 (0x00)
SRCDIV1–0
CLK2DIV1–0
CLK1DIV1–0
MCLKSEL1–0
Table 18. SPDIF Loop
ADDRESS = 0000011 (0x03)
TxMUX
Rev. 0 | Page 32 of 56
17. SRC and Cl
Control Register
1
SRCDIV
7
SRCDIV0
6
CLK2DIV1
5
CLK2DIV0
4
CLK1DIV1
3
CLK1DIV0
2
MCLKSEL1
1
MCLKSEL0
0
ock
Divides the SRC master clock.
00 = SRC master clock is not divided.
01 = SRC master clock
10 = SRC master clock is divided by 2.
11= SRC master cloc
Clock divid
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
is divided by 1.5.
k is divided by 3.
er for Internal Clock 2 (ICLK2).
Clock divider for Internal Clock 1 (ICLK1).
00 = Divide by 1.
01 = Divide by 1.5.
10 = D
2.
11
3.
Clock se
00 = Internal Clock 1.
01 = Internal Clock 2.
10 = PLL recovered clock (5
11 = PLL recovered clo
ivide by
= Divide by
lection for the SRC master clock.
12 × f
S
).
ck (256 × f
S
).
RES
6
RES
5
RES
4
RES
3
RES
2
RES
1
TxMUX
0
back Control Register
RES
7
Selects the source for SPDIF output (DITOUT).
0 = SPDIF transmitter, normal mode.
1 = DIRIN, loopback mode.
Table 19. Playback Port Control Register
ADDRESS = 0000100 (0x04)
CLKSRC1–0
SPMODE2–0
RES
7
RES
6
RES
5
CLKSRC1
4
CLKSRC0
3
SPMODE2
2
SPMODE1
1
SPMODE0
0
Selects the clock source for generating the ILRCLK and IBCLK.
00 = Input port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial format of the playback port.
000 = Left-justified.
001 = I
2
S.
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.
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