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參數(shù)資料
| 型號： | ADAV803ASTZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 23/56頁 |
| 文件大?。?/td> | 906K |
| 代理商： | ADAV803ASTZ-REEL |
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ADAV803
Rev. 0 | Page 23 of 56
0
PLL1 MCLK
PLL2 MCLK
48kHz
32kHz
44.1kHz
256
384
REG 0x75
BITS 3–2
REG 0x
BIT 0
REG 0x75
BIT 1
75
REG 0x77
BIT 0
PLL1
PLLINT1
SYSCLK1
×2
FS1
÷
2
REG 0x75
BIT 5
REG 0x75
BIT 4
REG 0x77
BITS 2–1
REG 0x75
BITS 7–6
BIT 0
PLL1
PLLINT1
SYSCLK2
REG 0x74
SYSCLK3
48kHz
32kHz
44.1kHz
256
38
4
×2
FS2
FS3
÷
2
÷
2
256
512
Figure 38. PLL Clocking Scheme
SPDIF TRANSMITTER AND RECEIVER
The ADAV803 contains an integrated SPDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
SPDIF transmitter source can be selected from the different
blocks making up the ADAV803. Additionally, the clock source
for the SPDIF transmitter can be selected from the various clock
sources available in the ADAV803.
The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts
the SPDIF input data stream. The DIRIN pin can be configured
to accept a digital input level, as defined in the Specifications
section, or an input signal with a peak-to-peak level of 200 mV
minimum, as defined by the IEC60958-3 specification. DIR_LF
is a loop filter pin, required by the internal PLL, which is used to
recover the clock from the SPDIF data stream.
The components shown in Figure 42 form a loop filter, which
integrates the current pulses from a charge pump and produces
a voltage that is used to tune the VCO of the clock recovery
PLL. The recovered audio data and audio clock can be routed to
the different blocks of the ADAV803, as required. Figure 39
shows a conceptual diagram of the DIRIN block.
C*
0
SPDIF
* EXTERNAL CAPACITOR IS ONLY REQUIRED
FOR VARIABLE LEVEL SPDIF INPUTS.
COMPARATOR
REG 0x74
BIT 4
DIRIN
DC
LEVEL
SPDIF
RECEIVER
Figure 39. DIRIN Block
0
DIT
INPUT
DIT
PLAYBACK
AUXILIARY IN
SRC
REG 0x63
BITS 2–0
ADC
DIR
DITOUT
Figure 40. Digital Output Transmitter Block Diagram
0
DIR
DIRIN
AUDIO
DATA
RECOVERED
CLOCK
Figure 41. Digital Input Receiver Block Diagram
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