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參數(shù)資料
| 型號： | ADAV400KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO80 |
| 封裝： | 14 X 14 MM, ROHS COMPLIANT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 446K |
| 代理商： | ADAV400KSTZ |
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ADAV400
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 36
2
VREF
3
AGND
4
AVDD1
7
NC
6
NC
5
NC
1
FILTA
8
NC
9
NC
10
NC
12
NC
13
DGND
14
DVDD
15
AD0
16
SDA
17
SCL
18
TEST0
19
TEST1
20
DGND
11
NC
59
58
57
54
55
56
60
53
52
VOUT2
VOUT1
AUXR1
HPOUTR
AVDD3
AUXL1
VOUT3
HPOUTL
AGND
51
AGND
49
AVDD2
48
DGND
47
DVDD
46
RESET
45
NC
44
NC
43
SDO3
42
SDO2
41
DGND
50
PLL_LF
NC = NO CONNECT
21
D
22
S
23
S
24
S
25
S
26
L
Figure 5. Pin Configuration
27
B
28
D
29
O
30
V
31
D
32
D
33
M
34
M
35
B
36
L
37
S
38
S
39
N
40
D
80
I
79
A
78
A
77
A
76
A
75
A
74
A
73
A
72
A
71
A
70
A
69
A
68
A
67
F
66
N
65
N
64
T
63
A
62
A
61
V
PIN 1
ADAV400
TOP VIEW
(Not to Scale)
0
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
FILTA
2
VREF
I/O
O
Description
ADC Filter Decoupling Node for the ADC. Decouple this pin to AGND (Pin 3).
Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin to AGND
(Pin 3)
ADC Ground. Connect this pin to the analog ground plane.
Analog Power Supply Pin for the ADC. Connect this pin to 3.3 V and decouple to AGND (Pin 3)
Not Connected Internally.
3
4
5 to 12,
65, 66
13, 20,
28, 32,
41, 48
14, 21,
31, 40,
47
15
AGND
AVDD1
NC
DGND
Digital Ground. Connect this pin to the digital ground plane.
DVDD
Digital Power Supply Pins. Connect these pins to 1.8 V, either directly or by using the on-chip regulator.
Decouple to DGND
AD0
I
I
2
C Address Select. Tie to ODVDD for address 0x28 (write) and 0x29 (read) or DGND for address 0x2A (write)
and 0x2B (read)
Serial Data Input/Output for the I
2
C Control Port.
Serial Clock for the I
2
C Control Port.
Test Pin. Connect to ODVDD.
Test Pin. Connect to ODVDD.
Serial Data Inputs. BCLK1 and LRCLK1 are used as the timing signals for SDIN0 to SDIN3.
Left/Right Clock for Sample Rate Converter (SRC). This input frame synchronization signal is associated
with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC.
Bit Clock for Sample Rate Converter (SRC). This input clock is associated with SDIN0 to SDIN3 when one of
these input channels is redirected to the SRC.
Digital Interface Supply (3.3 V) Pin. Connect this pin to a 3.3 V digital supply. Decouple to DGND.
Drive for External PNP Transistor. This is used with the on-chip 1.8 V regulator circuit
16
17
18
19
22 to 25
26
SDA
SCL
TEST0
TEST1
SDIN [0:3]
LRCLK0
I/O
I
I
I
27
BCLK0
I
29
30
ODVDD
VDRIVE
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