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參數(shù)資料
| 型號： | ADAV400KSTZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO80 |
| 封裝： | 14 X 14 MM, ROHS COMPLIANT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 446K |
| 代理商： | ADAV400KSTZ-REEL |
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ADAV400
Parameter
HEADPHONE OUTPUT (SINGLE-ENDED)
Rev. 0 | Page 5 of 36
Min
Typ
Max
Unit
Test Conditions/Comments
Measured at headphone output with 32 Ω load,
headphone amplifier register contents = 0x0001
One stereo channel
60 dBFS with respect to full-scale code input
3 dBFS with respect to full-scale code input
Relative to V
REF
1 kHz, 300 mV p-p signal at AVDDn
1
60 dBFS input (worst-case input f
S
= 50 kHz)
0 dBFS input (worst-case input f
S
= 50 kHz)
Number of Channels
Resolution
Full-Scale Analog Output
Dynamic Range
A-Weighted
Total Harmonic Distortion + Noise
Gain Error
Interchannel Gain Mismatch
DC Offset
Power Supply Rejection
PLL SECTION
2
Master Clock Input (MCLKI)
SRC
2
Dynamic Range
A-Weighted
Total Harmonic Distortion + Noise
Sample Rate
DIGITAL INPUT/OUTPUT
Input Voltage High (V
IH
)
Input Voltage Low (V
IL
)
Input Leakage (I
IH
@ V
IH
= ODVDD)
Input Leakage (I
IL
@ V
IL
= 0 V)
Output Voltage High (V
OH
@ I
OH
= 0.4
mA)
Output Voltage Low (V
OL
@ I
OL
= 3.2
mA)
Input Capacitance
SUPPLIES
Analog Supplies AVDDn
1
Digital Supplies DVDD
Interface Supply ODVDD
Supply Current, Normal Mode
Analog Current (AVDD1)
Digital and Interface Current
PLL Current
Supply Current, Power-Down Mode
Analog Current
Digital and Interface Current
PLL Current
1
The n refers to supply number, the m refers to channel number, and the Y refers to stereo channel identifier: L for left channel or R for right channel.
2
Guaranteed by design.
3
Measured on one DAC with other DACs and ADCs off.
64 × f
S
5
2.0
60
2
24
1
92
84
4
0.5
30
84
115
113
512 × f
S
50
ODVDD
0.8
10
Bits
V rms
dB
dB
%
dB
mV
dB
MHz
dB
dB
kHz
V
V
μA
μA
2.4
V
0.4
V
3.15
1.6
3.15
10
3.30
1.8
3.30
90
120
5
6
1.5
5
3.45
2.0
3.45
110
135
6
8.5
6
50
pF
V
V
V
mA
mA
mA
mA
mA
μA
MCLK = 12.288 MHz, ADCs and DACs active,
headphone outputs active and driving a 32 Ω load,
Power control register = 0xFFFF
RESET low, MCLK = 3.074 MHz, AINx = AGND, DAC
and headphone outputs floating
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