參數(shù)資料
型號(hào): ADAV400KSTZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: Audio Codec with Embedded SigmaDSP Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO80
封裝: 14 X 14 MM, ROHS COMPLIANT, MS-026BEC, LQFP-80
文件頁數(shù): 24/36頁
文件大小: 446K
代理商: ADAV400KSTZ-REEL
ADAV400
CONTROL PORT READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to be
byte-oriented. To conform to this byte-oriented format, 0s are
appended to the data fields before the MSB to extend the data-
word to the next multiple of eight bits. For example, for
parameter RAM a 28-bit word is appended with four leading 0s,
making the transfer 4 bytes; for program RAM a 42-bit word is
appended with six leading 0s, making the transfer 6 bytes. The
data fields are appended to a 3-byte field consisting of a 7-bit
Rev. 0 | Page 24 of 36
chip address, a read/write bit, and an 11-bit RAM/register
address for full I
2
C transfer.
Burst mode is used to fill contiguous register or RAM locations.
A burst mode write is done by writing the address and data of
the first RAM/register location to be written followed by the
next data-word, and so on. The ADAV400 control port auto-
increments the internal address counter depending on the
location being written to or read from, even across the
boundaries of the different RAMs and registers locations.
Table 16. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
chip_adr [6:0], R/W
000, param_adr [12:8]
Byte 2
param_adr [7:0]
Byte 3
0000, param [27:24]
Bytes 4 to 6
param [23:0]
Table 17. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
chip_adr [6:0], R/W
000, param_adr [12:8]
Byte 2
param_adr [7:0]
Byte 3
0000, param [27:24]
Bytes 4 to 6
param [23:0]
Bytes 7 to 10
0000 param [27:0]
Bytes 11 to 14
0000 param [27:0]
First parameter (param_adr)
Second parameter
(param_adr + 1)
Third parameter
(param_adr + 2)
Table 18. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
chip_adr [6:0], R/W
000, prog_adr [12:8]
Byte 2
prog_adr [7:0]
Bytes 3 to 8
prog [42:0]
Table 19. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
chip_adr [6:0], R/W
000, prog_adr [12:8]
Byte 2
prog_adr [7:0]
First program word (prog_adr)
Bytes 3 to 8
prog [39:0]
Bytes 9 to 14
Second program word
(prog_adr + 1)
Bytes 15 to 20
Third program word
(prog_adr + 2)
Table 20. Control Register Read/Write Format (16-bit register)
Byte 0
Byte1
chip_adr [6:0], R/W
000, reg_adr [12:8]
Byte 2
reg_adr [7:0]
Byte 3
data [15:8]
Byte 4
data [7:0]
Table 21. Control Register Read/Write Format (8-bit register)
Byte 0
Byte1
chip_adr [6:0], R/W
000, reg_adr [12:8]
Byte 2
reg_adr [7:0]
Byte 3
data [7:0]
Table 22. Data Capture Register Write Format
Byte 0
Byte 1
chip_adr [6:0], R/W
000, data_capture_adr [12:8]
Byte 2
data_capture_adr [7:0]
Byte 3
000, progCount [10:6]
Byte 4
progCount [5:0], regSel [1:0]
Table 23. Data Capture (Control Port Readback) Register Read Format
Byte 0
Byte 1
chip_adr [6:0], R/W
000, data_capture_adr [12:8]
Byte 2
data_capture_adr [7:0]
Bytes 3 to 5
data [23:0]
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