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參數(shù)資料
| 型號： | ADAV400 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | 音頻編解碼器與嵌入式的SigmaDSP處理器 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 446K |
| 代理商： | ADAV400 |
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ADAV400
Table 30. RAM Modulo Control Register (8 Bits)
Register Address 0x1053
Register Bits
Function
7:6
Reserved (set to 0)
5:0
RAM modulo size (1 LSB = 512 locations)
Rev. 0 | Page 29 of 36
Default = 0x28
Table 31. Serial Output Control Register
Register Address 0x1054
Register Bits
Function
15
Dither enable
0 = disabled
1 = enabled
14
TDM output mode
0 = 8-channel TDM
1 = 16-channel TDM
13
LRCLK polarity
0 = left low, right high
1 = left high, right low
12
BCLK polarity
0 = data changes on falling edge
1 = data changes on rising edge
11
Master/slave mode select
0 = slave
1 = master
10:9
BCLK frequency (master mode)
00 = 3.072 MHz (48 kHz)
01 = 6.144 MHz (96 kHz digital IO only)
10 = 12.288 MHz (192 kHz digital IO only)
11 = reserved
8:7
LRCLK frame sync frequency (master mode)
00 = 48 kHz
01 = 96 kHz
10 = 192 kHz
11 = reserved
6
Frame sync type
0 = LRCLK
1 = pulse
5
TDM enable
0 = serial data out
1 = TDM out
4:2
MSB position
000 = delay by 1
001 = delay by 0
010 = delay by 8
011 = delay by 12
100 = delay by 16
All others are reserved
1:0
Output Word length
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = 16 bits
Default = 0x0000
Table 32. Serial Input Control Register (8 Bits)
Register Address 0x1055
Register Bits
Function
7:6
Reserved (set to 0)
5
TDM input mode
0 = 8-channel TDM
1 = 16-channel TDM
4
LRCLK polarity
0 = left low, right high
1 = left high, right low
3
BCLK polarity
0 = data changes on falling edge
1 = data changes on rising edge
2:0
Serial input mode
000 = I
2
S
001 = left-justified
010 = 8-channel TDM
011 = right-justified, 24 bits
100 = right-justified, 20 bits
101 = right-justified, 18 bits
110 = right-justified, 16 bits
All others are reserved
Default = 0x00
Table 33. SRC Serial Port Control Register (8 Bits)
Register Address 0x1056
Register Bits
Function
7
Reserved (set to 0)
6:5
SRC serial input port select
00 = SDIN3
01 = SDIN2
10 = SDIN1
11 = SDIN0
4
LRCLK polarity
0 = left low, right high
1 = left high, right low
3
BCLK polarity
0 = data changes on falling edge
1 = data changes on rising edge
2:0
Serial input mode
000 = I
2
S
001 = left-justified
010 = reserved
011 = right-justified, 24 bits
100 = right-justified, 20 bits
101 = right-justified, 18 bits
110 = right-justified, 16 bits
All others are reserved
Default = 0x00
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| ADAV400KSTZ | Audio Codec with Embedded SigmaDSP Processor |
| ADAV400KSTZ-REEL | Audio Codec with Embedded SigmaDSP Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADAV400KSTZ | 制造商:Analog Devices 功能描述:AUD CODEC W/ EMBEDDED SIGMADSP PROCESSOR 80LQFP - Trays |
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| ADAV430 | 制造商:Analog Devices 功能描述:AUDIO PROCESSOR - Bulk |
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