參數(shù)資料
型號： ADAV400
廠商： Analog Devices, Inc.
元件分類： Codec
英文描述： Audio Codec with Embedded SigmaDSP Processor
中文描述： 音頻編解碼器與嵌入式的SigmaDSP處理器
文件頁數(shù)： 20/36頁
文件大?。?/td> 446K
代理商： ADAV400
ADAV400
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURES
When writing large amounts of data to the program or parameter
RAM in direct write mode, disable the processor core to prevent
pops or clicks at the audio output. The ADAV400 contains several
mechanisms for disabling the core.
Rev. 0 | Page 20 of 36
If the loaded program does not use the target/slew RAM as the
main system volume control (for example, the default power-up
program),
1.
Assert Bit 9 (low to assert—default setting) and Bit 6 (high
to assert) of the audio core control register. This clears the
accumulators, the serial output registers, and the serial
input registers.
Fill the program RAM using burst mode writes.
Fill the parameter RAM using burst mode writes.
Assert Bit 7 of the audio core control register to initiate a
data memory clear sequence. Wait at least 100 μs for this
sequence to complete. This bit is automatically cleared after
the operation is complete.
Deassert Bit 9 and Bit 6 of the audio core control register to
allow the core to begin normal operation
2.
3.
4.
5.
If the loaded program does use the target/slew RAM as the
main system volume control,
1.
Assert Bit 12 of the audio core control register. This begins
a volume ramp-down, with a time constant determined by
the upper bits of the target RAM. Wait for this ramp-down
to complete (the user can poll Bit 13 of the audio core
control register, or simply wait for a given amount of time).
Assert Bit 9 (low to assert) and Bit 6 (high to assert) of the
audio core control register. This clears the accumulators,
the serial output registers, and the serial input registers.
Fill the program RAM using burst mode writes.
Fill the parameter RAM using burst mode writes.
Assert Bit 7 of the audio core control register to initiate a
data memory clear sequence. Wait at least 100 μs for this
sequence to complete. This bit is automatically cleared after
the operation is complete.
Deassert Bit 9 and Bit 6 of the audio core control register.
If the newly loaded program also uses the target/slew RAM,
deassert Bit 12 of the audio core control register to begin a
volume ramp-up procedure.
2.
3.
4.
5.
6.
7.
TARGET/SLEW RAM
The target/slew RAM is a bank of 64 RAM locations, each of
which can be set to autoramp from one value to a desired final
value in one of four modes.
When a program is loaded into the program RAM using one or
more locations in the slew RAM to access internal coefficient
data, the target/slew RAM is used by the DSP. Typically, these
coefficients are used for volume controls or smooth cross-fading
effects, but they can also be used to update any value in the
parameter RAM. Each of the 64 locations in the slew RAM is
linked to corresponding location in the target RAM. When a new
value is written to the target RAM using the control port, the
corresponding slew RAM location begins to ramp toward the
target. The value is updated once per audio frame (LRCLK period).
The target RAM is 34 bits wide. The lower 28 bits contain the target
data in 5.23 format for the linear and exponential (constant dB
and RC) ramp types. For constant time ramping, the lower 28 bits
contain 16 bits in 2.14 format and 12 bits to set the current step.
The upper six bits are used to determine the type and speed of
the ramp envelope in all modes. The format of the data write for
linear and exponential formats is shown in Table 12. Table 13
shows the data write format for the constant time ramping.
In normal operation, write data to the target/slew RAM using
the safeload registers as described in the Safeload Registers
section. A mute slew RAM bit is included in the audio core
control register to simultaneously set all the slew RAM target
values to 0. This is useful for implementing a global multichannel
mute. When this bit is deasserted, all slew RAM values return to
their original premuted states.
Table 12. Linear, Constant dB, and RC Ramp Data Write
Byte 0
Byte 1
000000,
curve_type [1:0]
data [27:24]
Bytes [2:4]
data [23:0]
time_const [3:0],
Table 13. Constant Time Ramp Data Write
Byte 0
Byte 1
000000,
curve_type [1:0]
#_of_steps [2:0], data [15:12]
Bytes [2:4]
data [11:0],
reserved [11:0]
update_step [0],
There are four types of ramping curve:
Linear.
The value slews to the target value using a fixed step size.
Constant dB.
The value slews to the target value using the current value
to calculate the step size. The resulting curve has a constant
rise and decay when measured in decibels.
RC.
The value slews to the target value using the difference
between the target and current value to calculate the step
size, resulting in a simple RC response.
Constant Time.
The value slews to the target value in a fixed number of
steps in a linear fashion. The control port mute has no
effect on this type of ramping curve.
相關(guān)PDF資料
PDF描述
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