- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375252 > ADAU1701JSTZ (ANALOG DEVICES INC) SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | ADAU1701JSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 33/43頁(yè) |
| 文件大?。?/td> | 625K |
| 代理商： | ADAU1701JSTZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)
Preliminary Technical Data
ADAU1701
In TDM mode, the ADAU1701 can be a master for 48 kHz and
96 kHz data, but not for 192 kHz data. Table 43 displays the
modes in which the serial output port will function.
Table 43. Serial Output Port Master/Slave Mode Capabilities
f
S
2-Channel Modes
(I
2
S, LJ, RJ)
48 kHz
Master and slave
Rev. PrF | Page 33 of 43
8-Channel
TDM
Master and
slave
Master and
slave
Slave only
96 kHz
Master and slave
192 kHz
Master and slave
The output control registers give the user control of clock
polarities, clock frequencies, clock types, and data format. In all
modes except for the right-justified modes (MSB delayed by 8,
12, or 16), the serial port accepts an arbitrary number of bits up
to a limit of 24. Extra bits will not cause an error, but will be
truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers
correspond to 2-channel I
2
S mode. All register settings apply to
both master and slave modes unless otherwise noted.
The functions of the individual multi-purpose pins in serial
data port mode are shown in Table 44. Pins MP0-5 support
digital data input to the ADAU1701 and pins MP6-11 handle
digital data output from the DSP. The configuration of the serial
data input port is set in the Serial Input Control Register (Table
47) and the output port is controlled with the Serial Output
Control Register (Table 46). The input port clocks function only
as slaves and the output port clocks can be set to be either
master or slave. The INPUT_LRCLK and INPUT_BCLK pins
(MP4 & MP5) are used to clock the SDATA_INx signals (MP0-
3) and the OUTPUT_LRCLK and OUTPUT BCLK (MP10 &
MP11) are used to clock the SDATA_OUTx signals (MP6-9).
If an external ADC will be connected as a slave to the
ADAU1701, both the input and output port clocks will need to
be used. The output LRCLK and BCLK (MP10 & MP11) will
need to be set into master mode and connected externally to the
input LRCLK and BCLK pins (MP4 & MP5) and the external
ADC’s clock input pins. The data will be output from the
external ADC into the SigmaDSP on one of the four SDATA_IN
pins (MP0-3).
Connections to an external DAC are handled exclusively with
the output port pins. The output LRCLK and BCLK can be set
to be either master or slave, and the SDATA_OUT pins are used
to output data from the SigmaDSP to the external DAC.
Table 45 shows the proper configurations for standard audio
data formats.
Table 44. Multi-Purpose Pin Serial Data Port Functions
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
Function
SDATA_IN0/TDM_IN
SDATA_IN1
SDATA_IN2
SDATA_IN3
INPUT_LRCLK (slave only)
INPUT_BCLK (slave only)
SDATA_OUT0/TDM_OUT
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
OUTPUT_LRCLK (master or slave)
OUTPUT_BCLK (master or slave)
Table 45. Data Format Configurations
Format
I
2
S (Figure 32)
LRCLK Polarity
Frame begins on
falling edge
Frame begins on
rising edge
Frame begins on
rising edge
Frame begins on
falling edge
Frame begins on
rising edge
LRCLK Type
Clock
BCLK Polarity
Data changes on falling edge
MSB Position
Delayed from LRCLK edge by one BCLK
Left-Justified
(Figure 33)
Right-Justified
(Figure 34)
TDM with Clock
(Figure 35)
TDM with Pulse
(Figure 36)
Clock
Data changes on falling edge
Aligned with LRCLK edge
Clock
Data changes on falling edge
Delayed from LRCLK edge by 8, 12, or 16 BCLKs
Clock
Data changes on falling edge
Delayed from start of word clock by one BCLK
Pulse
Data changes on falling edge
Delayed from start of word clock by one BCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADAU1701JSTZ-RL | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| ADAV400 | Audio Codec with Embedded SigmaDSP Processor |
| ADAV400KSTZ | Audio Codec with Embedded SigmaDSP Processor |
| ADAV400KSTZ-REEL | Audio Codec with Embedded SigmaDSP Processor |
| ADAV803 | Audio Codec for Recordable DVD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1701JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1701MINIBZ | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| ADAU1702 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| ADAU1702JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1702JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。