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參數(shù)資料
| 型號： | ADAU1701JSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大?。?/td> | 625K |
| 代理商： | ADAU1701JSTZ |
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Preliminary Technical Data
ADAU1701
Rev. PrF | Page 11 of 43
DGND with a 100 nF capacitor.
Multi-Purpose – GPIO or Serial output port data 1 (SDATA_OUT1)
Multi-Purpose – GPIO, Serial output port data 0, or TDM data output
(SDATA_OUT0)
Multi-Purpose – GPIO or Serial output port LRCLK (OUTPUT_LRCLK)
Drive for 1.8 V regulator. The base of the voltage regulator’s external PNP
transistor is driven from VDRIVE.
Input and Output pins supply. The voltage on this pin sets the highest input
voltage that should be seen on the digital input pins. This pin is also the supply
for the digital output signals on the control port and MP pins. IOVDD should
always be set to 3.3 V. The current draw of this pin is variable because it is
dependant on the loads of the digital outputs.
Multi-Purpose – GPIO or Serial output port BCLK (OUTPUT_BCLK)
ADDR1: I
2
C Address 1, in combination with ADDR0 it will set the I
2
C address of
the IC. Four ADAU1701s to be used on the same I
2
C bus.
CDATA: SPI Data Input
WB: EEPROM Writeback trigger. A rising (default) or falling (if set in the EEPROM
messages) edge on this pin will trigger a write-back of the interface registers to
the external EEPROM. This function can be used to save parameter data on
power-down.
CLATCH: This SPI latch signal must go low at the beginning of an SPI transaction
and high at the end of a transaction. Each SPI transaction may take a different
number of CCLKs to complete, depending on the address and read/write bit that
are sent at the beginning of the SPI transaction.
WP: Self-boot EEPROM write protect. This pin is an open collector output when in
selfboot mode. The ADAU1701 will pull this low to prohibit writes to an external
EEPROM. This pin should be pulled high to 3.3 V.
SDA: This I
2
C data pin is a bidirectional open collector. The line connected to this
pin should have a 2.2 kΩ pull-up resistor.
COUT: This SPI data output is used for reading back registers and memory
locations. It is three-stated when an SPI read is not active.
SCL: This I
2
C clock pin is always an open collector input when in I
2
C control mode.
In self-boot mode this pin will be an open collector output (I
2
C master). The line
connected to this pin should have a 2.2 kΩ pull-up resistor.
CCLK: This SPI clock may either run continuously or be gated off in between SPI
transactions.
1.8 V Digital Supply. This can be supplied either externally or generated from a
3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to
DGND with a 100 nF capacitor.
DGND is a digital ground pin. The AGND, DGND, and PGND pins can be tied
directly together in a common ground plane. dGND should be decoupled to a
DVDD pin with a 100 nF capacitor.
Multi-Purpose – GPIO, serial output port data 3 (SDATA_OUT3), or auxiliary ADC
input 0
Multi-Purpose – GPIO, serial output port data 2 (SDATA_OUT2), or auxiliary ADC
input 3
Multi-Purpose – GPIO, serial input port data 3 (SDATA_IN3), or auxiliary ADC
input 2
Multi-Purpose – GPIO, serial input port data 2 (SDATA_IN2), or auxiliary ADC
input 1
Reserved, tie to ground, either directly or through a pull-down resistor.
OSCO is the output of the crystal oscillator circuit. A 100 Ω damping resistor
should be connected between this pin and the crystal. This output should not be
used to directly drive a clock to another IC. If the crystal oscillator is not used, this
pin can be left unconnected.
MCLKI can either be connected to a 3.3 V clock signal or can be the input from
the crystal oscillator circuit.
PGND is the PLL ground pin. The AGND, DGND, and PGND pins can be tied
directly together in a common ground plane. PGND should be decoupled to
14
15
D_IO
D_IO
MP7
MP6
16
17
D_IO
A_OUT
MP10
VDRIVE
18
PWR
IOVDD
19
20
D_IO
D_IN
MP11
ADDR1/CDATA/WB
21
D_IN
CLATCH / WP
22
D_IO
SDA/COUT
23
D_IO
SCL/CCLK
24
PWR
DVDD
25
PWR
DGND
26
D/A_IO
MP9
27
D/A_IO
MP8
28
D/A_IO
MP3
29
D/A_IO
MP2
30
31
X
D_OUT
RSVD
OSCO
32
D_IN
MCLKI
33
PWR
PGND
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| ADAU1701JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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| ADAU1702 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| ADAU1702JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1702JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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