參數(shù)資料
型號： ADAU1701JSTZ-RL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù)： 30/43頁
文件大小： 625K
代理商： ADAU1701JSTZ-RL
ADAU1701
Preliminary Technical Data
2
RegSel[1:0] selects one of four registers (see Data Capture Registers section).
Table 34. Data Capture (Control Port Readback) Register Read Format
Byte 0
Byte 1
chip_adr [6:0], W/R
0000, data_capture_adr[11:8]
Table 35. Safeload Address Register Write Format
Byte 0
Byte 1
chip_adr [6:0], W/R
0000, safeload_adr[11:8]
Table 36. Safeload Data Register Write Format
Byte 0
Byte 1
chip_adr [6:0], W/R
0000, safeload_adr[11:8]
DATA RAM
The ADAU1701’s data RAM is used to store audio data words
for processing. For the most part, this process is transparent to
the user; the user cannot even directly address this RAM space
from the control port. The size of the data RAM is 2 k words.
Rev. PrF | Page 30 of 43
Byte 2
data_capture_adr[7:0]
Bytes 3–5
data[23:0]
Byte 2
safeload_adr[7:0]
Byte 3
000000, param_adr[9:8]
Byte 4
param_adr[7:0]
Byte 2
safeload_adr[7:0]
Byte 3
00000000
Byte 4
0000, data[27:24]
Bytes 5–7
data[23:0]
The user’s only concern should be when implementing blocks
that utilize large amounts of data RAM space, such as delays.
The SigmaDSP core processes delay times in one-sample
increments, so the total pool of delay available to the user will
equal 2048 × the sample period. For fs = 48 kHz, this means
that the pool of available delay is a maximum of about 43 ms. In
practice, this much data memory will not be available to the
user, though, because every block in a design will use a few data
memory locations for its processing. In most DSP programs this
will not significantly impact the total delay time. The
SigmaStudio compiler will manage the data RAM and will
indicate if the number of addresses used has exceeded the
maximum available.
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