參數(shù)資料
型號： ADAU1445YSVZ-3A-RL
廠商： Analog Devices Inc
文件頁數(shù)： 52/92頁
文件大?。?/td> 0K
描述： IC SIGMADSP 175MHZ 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
ADAU1445/ADAU1446
Rev. A | Page 56 of 92
ASYNCHRONOUS SAMPLE RATE CONVERTERS
The integrated sample rate converters of the ADAU1445/
ADAU1446 processors can be configured in various ways to
facilitate asynchronous connectivity to other components in the
audio system. The sample rate converters operate completely
independent of the serial ports and DSP core, connecting via
the flexible audio routing matrix.
ASRC MODES AND SETTINGS
Table 34. Addresses of ASRC Modes Registers
Address
Name
Read/Write
Word Length
Decimal
Hex
57601
E101
Stereo ASRC[3:0] lock
status and mute
16 bits (2 bytes)
57603
E103
Stereo ASRC[3:0] mute
ramp disable
16 bits (2 bytes)
57665
E141
Stereo ASRC[7:4] lock
status and mute
16 bits (2 bytes)
57667
E143
Stereo ASRC[7:4] mute
ramp disable
16 bits (2 bytes)
Stereo ASRC[3:0] Lock Status and Mute Register
(Address 0xE101)
Table 35. Bit Descriptions of Register 0xE101
Bit
Position
Description
Default
[15:12]
Reserved
[11]
Stereo ASRC 3 (Channel 6, Channel 7)
lock status (read only)
0
[10]
Stereo ASRC 2 (Channel 4, Channel 5)
lock status (read only)
0
[9]
Stereo ASRC 1 (Channel 2, Channel 3)
lock status (read only)
0
[8]
Stereo ASRC 0 (Channel 0, Channel 1)
lock status (read only)
0
[7:4]
Reserved
[3]
Stereo ASRC 3 (Channel 6, Channel 7) mute
0
[2]
Stereo ASRC 2 (Channel 4, Channel 5) mute
0
[1]
Stereo ASRC 1 (Channel 2, Channel 3) mute
0
[0]
Stereo ASRC 0 (Channel 0, Channel 1) mute
0
Every sample rate converter pair for Stereo ASRC[3:0]) can be
muted. This function is controlled by a single 12-bit register.
The mute bits (Bits[3:0]) are active high; therefore, a value of 1
mutes the corresponding ASRC, and a value of 0 unmutes the
corresponding ASRC.
If the ASRC cannot find the ratio between the input and output
clock, the lock status bits (Bits[11:8]) are each set to 0, and the
ASRC automatically mutes itself. An ASRC mute can also be
manually initiated by setting the corresponding bit (Bits[3:0]) to
1. The muting is done with a volume ramp and is click and pop
free. If desired, the mute ramp can be disabled for Stereo
In the case of the ADAU1446, setting these registers does not
affect system operation in any way.
Stereo ASRC[3:0] Mute Ramp Disable Register
(Address 0xE103)
Table 36. Bit Descriptions of Register 0xE103
Bit
Position
Description
Default
[15:1]
Reserved
[0]
Stereo ASRC[3:0] (Channels[7:0]) mute ramp
disable
0
0 = enable ramp
1 = disable ramp
This single-bit register controls the behavior of Stereo ASRC[3:0]
(Channels[7:0]) on a loss of lock. When Bit 0 is set to the default
(0), Stereo ASRC[3:0] (Channels[7:0]) mute with a volume
ramp. When Bit 0 is set to 1, Stereo ASRC[3:0] mute abruptly.
In addition, setting this bit to 1 ignores the ASRC mute bits
(Bits[3:0]) in Register 0xE101 (see the Stereo ASRC[3:0] Lock
Status and Mute section); therefore, a mute only occurs on a
loss of lock.
In the case of the ADAU1446, setting this register does not
affect system operation in any way.
Stereo ASRC[7:4] Lock Status and Mute Register
(Address 0xE141)
Table 37. Bit Descriptions of Register 0xE141
Bit
Position
Description
Default
[15:12]
Reserved
[11]
Stereo ASRC 7 (Channel 14, Channel 15)
lock status (read only)
0
[10]
Stereo ASRC 6 (Channel 12, Channel 13)
lock status (read only)
0
[9]
Stereo ASRC 5 (Channel 10, Channel 11)
lock status (read only)
0
[8]
Stereo ASRC 4 (Channel 8, Channel 9)
lock status (read only)
0
[7:4]
Reserved
[3]
Stereo ASRC 7 (Channel 14, Channel 15) mute
0
[2]
Stereo ASRC 6 (Channel 12, Channel 13) mute
0
[1]
Stereo ASRC 5 (Channel 10, Channel 11) mute
0
[0]
Stereo ASRC 4 (Channel 8, Channel 9) mute
0
Every sample rate converter pair for Stereo ASRC[7:4] can be
muted. This function is controlled by a single 12-bit register.
The mute bits (Bits[3:0]) are active high; therefore, a value of 1
mutes the corresponding ASRC, and a value of 0 unmutes the
corresponding ASRC.
If the ASRC cannot find the ratio between the input and output
clock, the lock status bits (Bits[11:8]) are each set to 0, and the
ASRC automatically mutes itself. An ASRC mute can also be
manually initiated by setting the corresponding bit (Bits[3:0]) to 1.
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