參數(shù)資料
型號(hào)： ADAU1401YSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/52頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
ADAU1401
Data Sheet
Rev. C | Page 38 of 52
2064 TO 2068 (0x0810 TO 0x814)—SAFELOAD DATA REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multichannel virtualizing parameters, or dynamics
processing curves. When controlling a biquad filter, for
example, all of the parameters must be updated at the same
time. Doing so prevents the filter from executing with a mix of
old and new coefficients for one or two audio frames, thus
avoiding temporary instability and transients that may take a
long time to decay. To accomplish this, the ADAU1401 uses
safeload data registers to simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients and, as
previously mentioned, it is desirable to do a complete update in
one transaction.
The first step in performing a safeload operation is writing the
parameter address to one of the safeload address registers (2069
to 2073). The 10-bit data-word to be written is the address in
parameter RAM to which the safeload is being performed. After
this address is written, the 28-bit data-word can be written to
the corresponding safeload data register (2064 to 2068).
The data formats for these writes are detailed in Table 30 and
Table 31. Table 39 shows how each of the five address registers
maps to its corresponding data register.
After the address and data registers are loaded, set the initiate
safeload transfer bit in the core control register to initiate the
loading into RAM. Each of the five safeload registers takes one of
the 1024 core instructions to load into the parameter RAM. The
total program lengths should, therefore, be limited to 1019 cycles
(1024 minus 5) to ensure that the SigmaDSP core always has at
least five cycles available. The safeload is guaranteed to occur
within one LRCLK period (21 μs for a fS of 48 kHz) of the initiate
safeload transfer bit being set.
The safeload logic automatically sends data to be loaded into
RAM from only those safeload registers that have been written
to since the last safeload operation. For example, if two parameters
are to be updated in the RAM, only two of the five safeload registers
must be written. When the initiate safeload transfer bit is asserted,
only data from those two registers are sent to the RAM; the other
three registers are not sent to the RAM and may hold old or
invalid data.
Table 39. Safeload Address and Data Register Mapping
Safeload
Register
Safeload
Address Register
Safeload
Data Register
0
2069
2064
1
2070
2065
2
2071
2066
3
2072
2067
4
2073
2068
Table 40. Safeload Registers Bit Map
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
SD39
SD38
SD37
SD36
SD35
SD34
SD33
SD32
0x00
SD31
SD30
SD29
SD28
SD27
SD26
SD25
SD24
SD23
SD22
SD21
SD20
SD19
SD18
SD17
SD16
0x0000
SD15
SD14
SD13
SD12
SD11
SD10
SD09
SD08
SD07
SD06
SD05
SD04
SD03
SD02
SD01
SD00
0x0000
Table 41.
Bit Name
Description
SD[39:0]
Safeload Data. Data (program, parameters, register contents) to be loaded into the RAMs or
registers.
2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
Table 42. Safeload Address Registers Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
SA11
SA10
SA09
SA08
SA07
SA06
SA05
SA04
SA03
SA02
SA01
SA00
0x0000
Table 43.
Bit Name
Description
SA[11:0]
Safeload Address. Address of data that is to be loaded into the RAMs or registers.
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