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| 型號： | ADAU1401YSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO PROC 28/56BIT 48LQFP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 監(jiān)控器，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
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Data Sheet
ADAU1401
Rev. C | Page 27 of 52
SPI PORT
By default, the ADAU1401 is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of the ADAU1401 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
data should be written MSB first. The ADAU1401 cannot be
taken out of SPI mode without a full reset.
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1401s to share a CLATCH signal, yet still operate
independently. When ADDR0 is low, the chip address is 0000000;
when it is high, the address is 0000001 (see
). The LSB
of this first byte determines whether the SPI transaction is a
read (Logic Level 1) or a write (Logic Level 0).
Table 18. ADAU1401 SPI Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
ADDR0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register. The MSBs of the subaddress
are zero-padded to bring the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in Table 23 and
Table 25 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and the R/W bit and subsequent bytes carry the data.
Table 19. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
chip_adr[6:0], R/W
0000, subadr[11:8]
subadr[7:0]
data
1 Continues to end of data.
06
75
2
-0
2
6
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 26. SPI Write to ADAU1401 Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HIGH-Z
DATA
HIGH-Z
06
75
2-
0
27
BYTE 2
Figure 27. SPI Read from ADAU1401 Clocking (Single-Read Mode)
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| ADAU1401YSTZ-RL | 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1421YSTZ | 制造商:Analog Devices 功能描述: |
| ADAU1421YSTZ-REEL | 制造商:Analog Devices 功能描述: |
| ADAU1442 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Digital Audio Processor |
| ADAU1442YSVZ-3A | 功能描述:IC SIGMADSP 28B 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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