參數(shù)資料
型號(hào)： ADAU1401AWBSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/52頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
ADAU1401A
Rev. A | Page 17 of 52
INITIALIZATION
This section describes the procedure for properly setting up the
ADAU1401A. The following five-step sequence provides an
overview of how to initialize the IC:
1.
Apply power to the ADAU1401A.
2.
Wait for the PLL to lock.
3.
Load the SigmaDSP program and parameters.
4.
Set up registers (including multipurpose pins and digital
interfaces).
5.
Turn off the default muting of the converters, clear the
data registers, and initialize the DAC setup register (see
the Control Registers Setup section for specific settings).
To only test analog audio pass-through (ADCs to DACs), skip
Step 3 and Step 4 and use the default internal program.
POWER-UP SEQUENCE
The ADAU1401A has a built-in power-up sequence that initializes
the contents of all internal RAMs on power-up or when the device
is brought out of a reset. On the rising edge of RESET, the contents
of the internal program boot ROM are copied to the internal
program RAM memory, the parameter RAM is filled with values
(all 0s) from its associated boot ROM, and all registers are
initialized to 0s. The default boot ROM program copies audio
from the inputs to the outputs without processing it (see
). In this program, SDATA_IN0 and SDATA_IN1 are output
on DAC0 and DAC1 and on SDATA_OUT0 and
SDATA_OUT1. ADC0 and ADC1 are output on DAC2 and
DAC3. The data memories are also zeroed at power-up. New
values should not be written to the control port until the
initialization is complete.
Table 12. Power-Up Time
MCLKI Input
Frequency
Init.
Time
Maximum Program/
Parameter/Register
Boot Time (I2C)
Total
Time
3.072 MHz (64 × fS)
85 ms
175 ms
260 ms
11.2896 MHz (256 × fS)
23 ms
175 ms
198 ms
12.288 MHz (256 × fS)
21 ms
175 ms
196 ms
18.432 MHz (384 × fS)
16 ms
175 ms
191 ms
24.576 MHz (512 × fS)
11 ms
175 ms
186 ms
The PLL start-up time lasts for 218 cycles of the clock on the
MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz
(512 × fS) input clock to 85.3 ms for a 3.072 MHz (64 × fS) input
clock and is measured from the rising edge of RESET. Following
the PLL startup, the duration of the ADAU1401A boot cycle is
about 42 μs for a fS of 48 kHz. The user should avoid writing to or
reading from the ADAU1401A during this start-up time. For an
MCLKI input signal of 12.288 MHz, the full initialization sequence
(PLL startup plus boot cycle) is approximately 21 ms. As the device
comes out of a reset, the clock mode is immediately set by the
PLL_MODE0 and PLL_MODE1 pins. The reset is synchronized
to the falling edge of the internal clock.
Table 12 lists typical times to boot the ADAU1401A into an
operational state for an application, assuming a 400 kHz I2C
clock loading a full program, parameter set, and all registers
(about 8.5 kB). In reality, most applications do not fill the RAMs
and, therefore, boot time is less than the value listed in Column 3
CONTROL REGISTERS SETUP
The following registers must be set as described in this section
to initialize the ADAU1401A. These settings are the basic
minimum settings needed to operate the IC with an analog
input/output of 48 kHz. More registers may need to be set,
depending on the application. See the RAMs and Registers
section for additional settings.
DSP Core Control Register (Address 2076)
Set Bits[4:2] (ADM, DAM, and CR) each to 111.
DAC Setup Register (Address 2087)
Set Bits[1:0] (DS[1:0]) to 01.
RECOMMENDED PROGRAM/PARAMETER
LOADING PROCEDURE
When writing large amounts of data to the program or para-
meter RAM in direct write mode, the processor core should
be disabled to prevent unpleasant noises from appearing in
the audio output. To disable the processor core,
1.
Set Bits[4:3] (active low) of the DSP core control register
(Address 2076) to 1 to mute the ADCs and DACs. This
begins a volume ramp-down.
2.
Set Bit 2 (active low) of the DSP core control register to 1.
This zeroes the SigmaDSP accumulators, the data output
registers, and the data input registers.
3.
Fill the program RAM using burst mode writes.
4.
Fill the parameter RAM using burst mode writes.
5.
Set Bits[4:2] of the DSP core control register to 111.
ADC0
DAC1
DAC0
DAC2
DAC3
ADC1
SDATA_IN0
SDATA_OUT0
08
50
6-
01
3
Figure 13. Default Program Signal Flow
POWER REDUCTION MODES
Sections of the ADAU1401A chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
DACs, and voltage reference.
The individual analog sections can be turned off by writing to
the auxiliary ADC and power control register (Address 2082).
By default, the ADCs, DACs, and reference are enabled (all bits
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ADAU1401AWBSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1421YSTZ 制造商:Analog Devices 功能描述:
ADAU1421YSTZ-REEL 制造商:Analog Devices 功能描述:
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