參數(shù)資料
型號(hào)： ADAU1401AWBSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/52頁(yè)
文件大小： 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
ADAU1401A
Rev. A | Page 41 of 52
ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
Table 50. Serial Input Control Register Bit Map
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
ILP
IBP
M2
M1
M0
0x00
Table 51. Serial Input Control Register Bit Descriptions
Bit Name
Description
ILP
INPUT_LRCLK polarity. When this bit is set to 0, the left-channel data on the SDATA_INx pins is clocked when
INPUT_LRCLK is low and the right-channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1,
the clocking of these channels is reversed. In TDM mode when this bit is set to 0, data is clocked in, starting with
the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When
this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising
edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock.
In this case, the first edge of the pulse is used by the ADAU1401A to start the data frame. When this polarity bit
is set to 0, a low pulse should be used; when the bit it set to 1, a high pulse should be used.
IBP
INPUT_BCLK polarity. This bit controls on which bit clock edge the input data changes and on which edge it is
clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge when this
bit is set to 1.
Serial input mode. These three bits control the data format that the input port expects to receive. Bit 3 and Bit 4
of this control register override the settings of Bits[2:0]; therefore, all five bits must be changed together for
proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and
Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is
the opposite of the default setting for the ILP bit.
When these bits are set to accept a TDM input, the ADAU1401A data starts after the edge defined by ILP. The
ADAU1401A TDM data stream should be input on Pin SDATA_IN0. Figure 35 shows a TDM stream with a high-to-
low triggered LRCLK and data changing on the falling edge of the BCLK. The ADAU1401A expects the MSB of
each data slot to be delayed by one BCLK from the beginning of the slot, as it would in stereo I2S format. In TDM
mode, Channel 0 to Channel 3 are in the first half of the frame, and Channel 4 to Channel 7 are in the second
half. Figure 36 shows an example of a TDM stream running with a pulse word clock, which is used to interface to
Analog Devices codecs in auxiliary mode. To work in this mode with either the input or output serial ports, set the
ADAU1401A to begin the frame on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to
delay the MSB position from the start of the word clock by one BCLK.
Settings
Function
000
I2S
001
Left-justified
010
TDM
011
Right-justified, 24 bits
100
Right-justified, 20 bits
101
Right-justified, 18 bits
110
Right-justified, 16 bits
M[2:0]
111
Reserved
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ADAU1401AWBSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1421YSTZ 制造商:Analog Devices 功能描述:
ADAU1421YSTZ-REEL 制造商:Analog Devices 功能描述:
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