參數(shù)資料
型號(hào): ADATE205BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 7/16頁
文件大小: 0K
描述: IC DCL DUAL 250MHZ ATE 100TQFP
標(biāo)準(zhǔn)包裝: 1
類型: 有源負(fù)載(DCL),比較器,驅(qū)動(dòng)器
應(yīng)用: 自動(dòng)測試設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 管件
ADATE205
Rev. A | Page 15 of 16
THEORY OF OPERATION
The ADATE205 has two general classes of logic inputs:
differential inputs for controlling functions that generally need
to be operated at high speed, and single-ended CMOS inputs
for setting operating modes or other low speed functions. The
differential inputs have a wide common-mode range that allows
them to be used with a variety of logic families. The differential
inputs can also be used single-ended, with one input from each
pair of inputs tied to a fixed reference, but this makes precise
timing more difficult to achieve.
These differential input pins provide 50 Ω input termination
resistors for use as desired. The single-ended inputs have an
input range compatible with most logic families and are high
impedance to make driving them very easy. The switching
threshold for the single-ended inputs is preset to one-half of the
voltage at the CMOS_VDD pin.
Table 4. Driver and Load Modes
LDEN
(CMOS Single-Ended)
VTEN
(CMOS Single-Ended)
DR_EN
(High Speed Differential)
DR_DATA
(High Speed Differential)
Driver
Status
Load
Status
0
X
High-Z
0
1
0
VIL
High-Z
0
1
VIH
High-Z
0
1
0
X
VIT
High-Z
0
1
0
VIL
High-Z
0
1
VIH
High-Z
1
0
X
High-Z
ON
1
0
1
0
VIL
High-Z
1
0
1
VIH
High-Z
Table 5. Comparator Low Leakage Mode
CLLM (CMOS Single-Ended)
Typical DUT Pin Bias Current
0
1 μA
1
10 nA
Table 6. Rise/Fall Time Selection 3 V, 10% to 90%, Unterminated
Slew 1
Slew 0
Tr/Tf (ns)
0
1.4
0
1
1.9
1
0
2.8
1
5.6
Table 7. Comparator Logic Function
DUT Pin Voltage
Output States
COMP_L_P
COMP_L_N
COMP_H_P
COMP_H_N
>CVL
>CVH
1
0
1
0
>CVL
<CVH
1
0
1
<CVL
>CVH
0
1
0
<CVL
<CVH
0
1
0
1
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