ADATE205
Rev. A | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 10 V, VEE = 5 V, TJ = 75°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Single-Ended Logic Input Characteristics
(VTEN, DRV_INV)
Threshold Voltage
CMOS_VDD/2
V
Voltage Range
0
5.5
V
Bias Current
10
+10
μA
VIN = 0 V, 3.3 V
Single-Ended Logic Input Characteristics
(SLEW0, SLEW1)
Threshold Voltage
CMOS_VDD/2
V
Voltage Range
0
5.5
V
Bias Current
10
+600 (@ 3.3 V)
+800
μA
VIN = 0 V, 3.3 V
Bias Current
1
mA
VIN = 5.5 V
Differential Logic Input Characteristics
(DR_DATA_N, DR_DATA_P, DR_EN_N,
DR_EN_P)
Voltage Range
2.0
+3.5
V
Differential Voltage with LVPECL Levels
±250
±300
mV
Bias Current
10
+2
+10
μA
VIN = 3.24 V, 3.495 V
VIH, VIL Reference Inputs
Input Bias Current
10
2
+10
μA
Maximum value bias of
reference sweep
VIT Reference Inputs
Input Bias Current
25
+12
+25
μA
Maximum value bias of
reference sweep
DC Output Characteristics
Logic Range, VIL, VIH, VIT
1.5
+6.5
V
Amplitude [VH to VL]
8
V
Output Resistance
47.5
52.5
Ω
PSRR, Drive or Term Mode
10
mV/V
VCC, VEE ±1%
Static Current Limit
125
±110
+125
mA
Output to 1.5 V, VH = 6.5 V,
VT = 0 V
Absolute Accuracy—VIH, VIL, VIT
VIH Offset
100
+30
+100
mV
Data = H, VH = 0 V, VL = 1.5 V,
VT = 3 V
VIH Gain Error
0.98
1.02
V/V
Data = H, VH = 0 V to 5 V,
VL = 1.5 V, VT = 3 V
VIH Linearity Error
15
+5
+15
mV
Data = VH relative to line
between 0 V to 5 V; full range of
VIH = 1.4 V to +6.5 V
VIL Offset
100
+30
+100
mV
VIL Gain Error
0.98
1.02
V/V
Data = L, VL = 0 V to 5 V,
VH = 6.5 V, VT = 3 V
VIL Linearity Error
15
+5
+15
mV
Data = VH relative to line
between 0 V to 5 V; full range of
VIH = 1.4 V to +6.5 V
VIT Offset
100
+30
+100
mV
Data = VT, VT = 0 V, VL = 0 V,
VH = 3 V
VIT Gain Error
0.98
1.02
V/V
Data = VT, VT = 0 V to 5 V,
VL = 0 V, VH = 3 V