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參數(shù)資料
| 型號： | ADA4938-2ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DRIVER DUAL DIFF 24LFCSP |
| 標準包裝： | 5,000 |
| 類型： | ADC 驅動器 |
| 應用： | 數(shù)據(jù)采集 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
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ADA4938-1/ADA4938-2
Rev. A | Page 20 of 28
)
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and IN by the appropriate output factor,
where:
(
2
1
N
β
G
+
=
2
is the circuit noise gain.
G1
F1
G1
1
R
β
+
=
and
G2
F2
G2
2
R
β
+
=
are the feedback factors.
When RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain
becomes
G
F
N
R
β
G
+
=
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
∑
=
8
1
i
2
nOi
nOD
v
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional op amp.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = +1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-case
input CMRR of about 40 dB, a worst-case differential-mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
(+DIN and DIN) is simply RIN, dm = 2 × RG.
+VS
ADA4938
+IN
–IN
RF
+DIN
–DIN
VOCM
RG
VOUT, dm
06
59
2-
0
06
Figure 59. ADA4938 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 60),
the input impedance is
()
+
×
=
F
G
F
G
cm
IN
R
2
1
,
RT
RS
ADA4938
+VS
RF
RG
RS
RG
RF
VOCM
RT
VOUT, dm
06
59
2-
00
7
Figure 60. ADA4938-x Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4938 is optimized for level-shifting, ground-referenced
input signals. As such, the center of the input common-mode
range is shifted approximately 1 V down from midsupply. The
input common-mode range at the summing nodes of the amplifier
is from 0.3 V above VS to 1.6 V below +VS. To avoid clipping at
the outputs, the voltage swing at the +IN and IN terminals must
be confined to these ranges.
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