參數(shù)資料
型號(hào)： ADA4841-2YRZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF R-R DUAL LP LN 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 電壓反饋
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 13 V/µs
-3db帶寬： 80MHz
電流 - 輸入偏壓： 3µA
電壓 - 輸入偏移： 40µV
電流 - 電源： 1.2mA
電流 - 輸出 / 通道： 60mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 12 V，±1.35 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
ADA4841-1/ADA4841-2
Rev. E | Page 15 of 20
Figure 45 shows the amplifier frequency response as a G = 1
inverter with the input and output stage biased near the
negative supply rail.
6
–12
0.1
100
05614-
017
FREQUENCY (MHz)
GAIN
(
d
B)
110
3
0
–3
–6
–9
VS+ = 5V
G = –1
VIN = 20mV p-p
VS– = –50mV
VS– = –100mV
VS– = –200mV
VS– = –20mV
VS– = –150mV
Figure 45. Small Signal Frequency Response vs. Negative Supply Bias
The input voltage (VIN) and reference voltage (VIP) are both at
0 V, (see Figure 39). +VS is biased at +5 V, and VS is swept
from 200 mV to 20 mV. With the input and output voltages
biased 200 mV above the bottom rail, the G = 1 inverter
frequency response is not much different from what is seen
with the input and output voltages biased near midsupply.
At 150 mV bias, the frequency response starts to decrease
and at 20 mV, the inverter bandwidth is less than half its
nominal value.
CAPACITANCE DRIVE
Capacitance at the output of an amplifier creates a delay within
the feedback path that, if within the bandwidth of the loop, can
create excessive ringing and oscillation. The G = +1 follower
topology has the highest loop bandwidth of any typical
configuration and, therefore, is the most vulnerable to the
effects of capacitance load.
A small resistor in series with the amplifier output and the
capacitive load mitigates the problem. Figure 46 plots the
recommended series resistance vs. capacitance for gains
of +1, +2, and +5.
60
0
10
10000
05614-
050
CAPACITANCE LOAD (pF)
SERIES
RESISTANCE
(Ω
)
50
40
30
20
10
100
1000
G = +1
G = +2
G = +5
Figure 46. Series Resistance vs. Capacitance Load
INPUT PROTECTION
The ADA4841-1/ADA4841-2 are fully protected from ESD
events, withstanding human body model ESD events of 2.5 keV
and charge device model events of 1 keV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 47.
05614-
006
VP
ESD
VEE
VCC
BIAS
TO REST OF AMPLIFIER
VN
ESD
Figure 47. Input Stage and Protection Diodes
For differential voltages above approximately 1.4 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages need to be
sustained across the input terminals, it is recommended that the
current through the input clamps be limited to below 150 mA.
Series input resistors sized appropriately for the expected
differential overvoltage provide the needed protection.
The ESD clamps start to conduct for input voltages more than
0.7 V above the positive supply and input voltages more than
0.7 V below the negative supply. It is recommended that the
fault current be limited to less than 150 mA if an overvoltage
condition is expected.
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