參數(shù)資料
型號(hào)： ADA4841-2YRZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF R-R DUAL LP LN 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 電壓反饋
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 13 V/µs
-3db帶寬： 80MHz
電流 - 輸入偏壓： 3µA
電壓 - 輸入偏移： 40µV
電流 - 電源： 1.2mA
電流 - 輸出 / 通道： 60mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 12 V，±1.35 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
ADA4841-1/ADA4841-2
Rev. E | Page 13 of 20
THEORY OF OPERATION
AMPLIFIER DESCRIPTION
The ADA4841-1/ADA4841-2 are low power, low noise,
precision voltage-feedback op amps for single or dual voltage
supply operation. The ADA4841-1/ADA4841-2 are fabricated
on ADI’s second generation XFCB process and feature trimmed
supply current and offset voltage. The 2.1 nV/√Hz voltage noise
(very low for a 1.1 mA supply current amplifier), 40 μV offset
voltage, and sub 1 μV/°C offset drift is accomplished with an
input stage made of an undegenerated PNP input pair driving a
symmetrical folded cascode. A rail-to-rail output stage provides
the maximum linear signal range possible on low voltage
supplies and has the current drive capability needed for the
relatively low resistance feedback networks required for low
noise operation. CMRR, PSRR, and open-loop gain are all
typically above 100 dB, preserving the precision performance in
a variety of configurations. Gain bandwidth is kept high for this
power level to preserve the outstanding linearity performance
for frequencies up to 100 kHz. The ADA4841-1 has a power-
down function to further reduce power consumption. All this
results in a low noise, power efficient, precision amplifier that is
well-suited for high resolution and precision applications.
DC ERRORS
Figure 39 shows a typical connection diagram and the major dc
error sources. The ideal transfer function (all error sources set
to 0 and infinite dc gain) can be written as
IN
G
F
IP
G
F
OUT
V
R
V
R
V
×
×
+
= 1
(1)
05614-
004
RG
– VIN +
RS
– VIP +
IB+
IB–
+ VOUT –
RF
+ VOS –
Figure 39. Typical Connection Diagram and DC Error Sources
This reduces to the familiar forms for inverting and
noninverting op amp gain expressions
IP
G
F
OUT
V
R
V
×
+
= 1
(2)
(Noninverting gain, VIN = 0 V)
IN
G
F
OUT
V
R
V
×
=
(3)
(Inverting gain, VIP = 0 V)
The total output voltage error is the sum of errors due to the
amplifier offset voltage and input currents. The output error
due to the offset voltage can be estimated as
+
×
+
+
=
G
F
OUT
PNOM
P
OFFSET
OUT
R
A
V
PSRR
V
CMRR
VCM
V
NOM
ERROR
1
(4)
where:
NOM
OFFSET
V
is the offset voltage at the specified supply voltage.
This is measured with the input and output at midsupply.
VCM is the common-mode voltage.
VP is the power supply voltage.
NOM
p
V
is the specified power supply voltage.
CMRR is the common-mode rejection ratio.
PSRR is the power supply rejection ratio.
A is the dc open-loop gain.
The output error due to the input currents can be estimated as
+
×
+
×
+
×
=
B
G
F
S
B
G
F
G
F
OUT
I
R
I
R
V
ERROR
1
)
||
(
(5)
Note that setting RS equal to RF||RG compensates for the voltage
error due to the input bias current.
NOISE CONSIDERATIONS
Figure 40 illustrates the primary noise contributors for the
typical gain configurations. The total rms output noise is
the root-mean-square of all the contributions.
0
56
14-
0
05
RG
RS
ien
+ vout_en –
RF
ven
4kT × RS
vn _ RS =
4kT × RG
vn _ RG =
4kT × RF
vn _ RF =
Figure 40. Noise Sources in Typical Connection
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