VSY
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ADA4051-2ACPZ-R7
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 14/20闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC OPAMP RRIO ZERO DRIFT 8LFCSP
妯欐簴鍖呰锛� 1,500
鏀惧ぇ鍣ㄩ鍨嬶細 闆舵紓绉�
闆昏矾鏁�(sh霉)锛� 2
杓稿嚭椤炲瀷锛� 婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 0.06 V/µs
澧炵泭甯跺绌嶏細 125kHz
闆绘祦 - 杓稿叆鍋忓锛� 20pA
闆诲 - 杓稿叆鍋忕Щ锛� 2µV
闆绘祦 - 闆绘簮锛� 13µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 15mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 1.8 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-VFDFN 瑁搁湶鐒婄洡锛孋SP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-LFCSP-VD锛�3x3锛�
鍖呰锛� 甯跺嵎 (TR)
ADA4051-1/ADA4051-2
Rev. B | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS鈥�1.8 V OPERATION
VSY = 1.8 V, VCM = VSY/2 V, TA = 25掳C, RL = 100 k惟 to GND, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
ADA4051-2
0 V 鈮� VCM 鈮� 1.8 V
2
15
渭V
ADA4051-1
0 V 鈮� VCM 鈮� 1.8 V
2
17
渭V
Offset Voltage Drift
VOS/T
40掳C 鈮� TA 鈮� +125掳C
0.02
0.1
渭V/掳C
Input Bias Current
IB
5
50
pA
40掳C 鈮� TA 鈮� +125掳C
200
pA
Input Offset Current
IOS
10
100
pA
40掳C 鈮� TA 鈮� +125掳C
150
pA
Input Voltage Range
40掳C 鈮� TA 鈮� +125掳C
0
1.8
V
Common-Mode Rejection Ratio
CMRR
0 V 鈮� VCM 鈮� 1.8 V
105
125
dB
40掳C 鈮� TA 鈮� +125掳C
100
dB
Large-Signal Voltage Gain
AVO
RL = 10 k惟 to VCM,
0.1 V 鈮� VOUT 鈮� VSY 0.1 V
106
130
dB
40掳C 鈮� TA 鈮� +125掳C
100
dB
Input Resistance
RIN
8
M惟
Input Capacitance, Differential Mode
CINDM
2
pF
Input Capacitance, Common Mode
CINCM
5
pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 k惟 to VCM
1.796
1.799
V
40掳C 鈮� TA 鈮� +125掳C
1.79
V
RL = 10 k惟 to VCM
1.76
1.796
V
40掳C 鈮� TA 鈮� +125掳C
1.7
V
Output Voltage Low
VOL
RL = 100 k惟 to VCM
1
3
mV
40掳C 鈮� TA 鈮� +125掳C
9
mV
RL = 10 k惟 to VCM
3
20
mV
40掳C 鈮� TA 鈮� +125掳C
40
mV
Short-Circuit Current
ISC
VOUT = VSY or GND
13
mA
Closed-Loop Output Impedance
ZOUT
f = 1 kHz, G = 10
1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
1.8 V 鈮� VSY 鈮� 5.5 V
110
135
dB
40掳C 鈮� TA 鈮� +125掳C
106
dB
Supply Current per Amplifier
ISY
ADA4051-2
VOUT = VSY/2
13
17
渭A
ADA4051-1
VOUT = VSY/2
15
18
渭A
40掳C 鈮� TA 鈮� +125掳C
20
渭A
DYNAMIC PERFORMANCE
Slew Rate
SR+
RL = 10 k惟, CL = 100 pF, G = 1
0.04
V/渭s
SR
RL = 10 k惟, CL = 100 pF, G = 1
0.03
V/渭s
Settling Time
tS
To 0.1%, VIN = 1 V p-p,
RL = 10 k惟, CL = 100 pF
120
渭s
Gain Bandwidth Product
GBP
CL = 100 pF, G = 1
115
kHz
Phase Margin
M
CL = 100 pF, G = 1
40
Degrees
Channel Separation
CS
VIN = 1.7 V, f = 100 Hz
140
dB
NOISE PERFORMANCE
Voltage Noise
en p-p
f = 0.1 Hz to 10 Hz
1.96
渭V p-p
Voltage Noise Density
en
f = 1 kHz
95
nV/鈭欻z
Current Noise Density
in
f = 1 kHz
100
fA/鈭欻z
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