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參數(shù)資料
| 型號： | AD9992BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 托盤 |
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AD9992
Rev. C | Page 25 of 92
HBLK Mode 2 Operation
HBLK Mode 2 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced apart
from one another are needed, HBLK Mode 2 can be used. Using
a separate set of registers, HBLK Mode 2 can divide the HBLK
region into up to six repeat areas (see Table 11). As shown in
Figure 30, each repeat area shares a common group of toggle
positions, HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC.
However, the number of toggles following each start position
can be unique in each repeat area by using the RA*H1REP* and
RA*H2REP* registers. As shown in Figure 29, setting the
RA*H1REPA/RA*H1REPB/RA*H1REPC or RA*H2REPA/
RA*H2REPB/RA*H2REPC registers to 0 masks HCLK groups
from appearing in a particular repeat area. Figure 30 shows only
two repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 30 shows an example of RA0H1REPA/RA0H1REPB/
RA0H1REPC = RA0H2REPA/RA0H2REPB/RA0H2REPC =
RA1H1REPA/RA1H1REPB/RA1H1REPC = RA1H2REPA/
RA1H2REPB/RA1H2REPC = 2.
Furthermore, HBLK Mode 2 allows a different HBLK pattern
on even and odd lines. The HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC registers, as well as the RA*H1REPA/RA*H1REPB
/RA*H1REPC and RA*H2REPA/ RA*H2REPB/RA*H2REPC
registers, define operation for the even lines. For separate
control of the odd lines, the HBLKALT_PAT registers specify
up to six repeat areas on the odd lines by reordering the repeat
areas used for the even lines. New patterns are not available, but
the order of the previously defined repeat areas on the even lines
can be changed for the odd lines to accommodate advanced
CCD operation.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 31 shows an example CCD layout. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
Figure 32 shows the basic sequence layout to be used during
the effective pixel readout. The 48 OB pixels at the end of each
line are used for the CLPOB signals. PBLK is optional and is
often used to blank the digital outputs during the HBLK time.
HBLK is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK impacts the accuracy of the CLPOB
circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes,
such as adding in a separate sequence to clamp in the entire
shield OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPMASK registers are also useful for disabling the CLPOB
on a few lines without affecting the setup of the clamping
sequences. It is important that CLPOB be used only during valid
OB pixels. During other portions on the frame timing, such as
vertical blanking or SG line timing, the CCD does not output
valid OB pixels. Any CLPOB pulse that occurs during this time
causes errors in clamping operation and changes in the black
level of the image.
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
V
H
05
89
1-
03
1
Figure 31. Example CCD Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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